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ICache: Change cache_data to block RAM (yay!).
[firearm.git] / tests / anulib.S
1         .text
2         .globl _start
3 _start:
4         ldr sp, =0x3FFC
5         bl main
6 1:      b 1b
7
8         .globl putc
9 putc:
10         mcr 5, 0, r0, c0, c0
11         mov pc, lr
FireARM pipelined ARM-like CPU implementation in Verilog
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