memory: preliminary, regfile: more read port, decode: more correct
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         input [31:0] inspsr,
9         output reg [31:0] op0,
10         output reg [31:0] op1,
11         output reg [31:0] op2,
12         output reg carry,
13         output reg [31:0] outspsr,
14
15         output reg [3:0] read_0,
16         output reg [3:0] read_1,
17         output reg [3:0] read_2,
18         input [31:0] rdata_0,
19         input [31:0] rdata_1,
20         input [31:0] rdata_2
21         );
22
23         wire [31:0] regs0, regs1, regs2;
24         reg [31:0] rpc;
25         reg [31:0] op0_out, op1_out, op2_out;
26         reg carry_out;
27
28         /* shifter stuff */
29         wire [31:0] shift_oper;
30         wire [31:0] shift_res;
31         wire shift_cflag_out;
32         wire [31:0] rotate_res;
33
34         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
35         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
36         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
37
38         IREALLYHATEARMSHIFT shift(.insn(insn),
39                                   .operand(regs1),
40                                   .reg_amt(regs2),
41                                   .cflag_in(incpsr[`CPSR_C]),
42                                   .res(shift_res),
43                                   .cflag_out(shift_cflag_out));
44
45         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
46                               .amt(insn[11:8]),
47                               .res(rotate_res));
48
49         always @(*)
50                 casez (insn)
51                 `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
52 //              `DECODE_ALU_MUL_LONG,           /* Multiply long */
53                 `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
54                 `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
55                 `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
56                 `DECODE_ALU_SWP,                /* Atomic swap */
57                 `DECODE_ALU_BX,                 /* Branch and exchange */
58                 `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
59                 `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
60                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
61                 `DECODE_LDRSTR,                 /* Single data transfer */
62                 `DECODE_LDMSTM,                 /* Block data transfer */
63                 `DECODE_BRANCH,                 /* Branch */
64                 `DECODE_LDCSTC,                 /* Coprocessor data transfer */
65                 `DECODE_CDP,                    /* Coprocessor data op */
66                 `DECODE_MRCMCR,                 /* Coprocessor register transfer */
67                 `DECODE_SWI:                    /* SWI */
68                         rpc = inpc + 8;
69                 `DECODE_ALU:                    /* ALU */
70                         rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
71                 default:                        /* X everything else out */
72                         rpc = 32'hxxxxxxxx;
73                 endcase
74         
75         always @(*) begin
76                 read_0 = 4'hx;
77                 read_1 = 4'hx;
78                 read_2 = 4'hx;
79                 
80                 op0_out = 32'hxxxxxxxx;
81                 op1_out = 32'hxxxxxxxx;
82                 op2_out = 32'hxxxxxxxx;
83                 carry_out = 1'bx;
84                 
85                 casez (insn)
86                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
87                 begin
88                         read_0 = insn[15:12]; /* Rn */
89                         read_1 = insn[3:0];   /* Rm */
90                         read_2 = insn[11:8];  /* Rs */
91                         
92                         op0_out = regs0;
93                         op1_out = regs1;
94                         op2_out = regs2;
95                 end
96 //              `DECODE_ALU_MUL_LONG:   /* Multiply long */
97 //              begin
98 //                      read_0 = insn[11:8]; /* Rn */
99 //                      read_1 = insn[3:0];   /* Rm */
100 //                      read_2 = 4'b0;       /* anyus */
101 //
102 //                      op1_res = regs1;
103 //              end
104                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
105                 begin end
106                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
107                 begin
108                         read_0 = insn[3:0];     /* Rm */
109                         
110                         op0_out = regs0;
111                 end
112                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
113                 begin
114                         read_0 = insn[3:0];     /* Rm */
115                         
116                         if(insn[25]) begin     /* the constant case */
117                                 op0_out = rotate_res;
118                         end else begin
119                                 op0_out = regs0;
120                         end
121                 end
122                 `DECODE_ALU_SWP:        /* Atomic swap */
123                 begin
124                         read_0 = insn[19:16]; /* Rn */
125                         read_1 = insn[3:0];   /* Rm */
126                         
127                         op0_out = regs0;
128                         op1_out = regs1;
129                 end
130                 `DECODE_ALU_BX:         /* Branch and exchange */
131                 begin
132                         read_0 = insn[3:0];   /* Rn */
133                         
134                         op0_out = regs0;
135                 end
136                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
137                 begin
138                         read_0 = insn[19:16];
139                         read_1 = insn[3:0];
140                         
141                         op0_out = regs0;
142                         op1_out = regs1;
143                 end
144                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
145                 begin
146                         read_0 = insn[19:16];
147                         
148                         op0_out = regs0;
149                         op1_out = {24'b0, insn[11:8], insn[3:0]};
150                 end
151                 `DECODE_ALU:            /* ALU */
152                 begin
153                         read_0 = insn[19:16]; /* Rn */
154                         read_1 = insn[3:0];   /* Rm */
155                         read_2 = insn[11:8];  /* Rs for shift */
156                         
157                         op0_out = regs0;
158                         if(insn[25]) begin     /* the constant case */
159                                 carry_out = incpsr[`CPSR_C];
160                                 op1_out = rotate_res;
161                         end else begin
162                                 carry_out = shift_cflag_out;
163                                 op1_out = shift_res;
164                         end
165                 end
166                 `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
167                 begin
168                         /* eat shit */
169                 end
170                 `DECODE_LDRSTR:         /* Single data transfer */
171                 begin
172                         read_0 = insn[19:16]; /* Rn */
173                         read_1 = insn[3:0];   /* Rm */
174                         
175                         op0_out = regs0;
176                         if(insn[25]) begin
177                                 op1_out = {20'b0, insn[11:0]};
178                                 carry_out = incpsr[`CPSR_C];
179                         end else begin
180                                 op1_out = shift_res;
181                                 carry_out = shift_cflag_out;
182                         end
183                 end
184                 `DECODE_LDMSTM:         /* Block data transfer */
185                 begin
186                         read_0 = insn[19:16];
187                         
188                         op0_out = regs0;
189                         op1_out = {16'b0, insn[15:0]};
190                 end
191                 `DECODE_BRANCH:         /* Branch */
192                 begin
193                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
194                 end
195                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
196                 begin
197                         read_0 = insn[19:16];
198                         
199                         op0_out = regs0;
200                         op1_out = {24'b0, insn[7:0]};
201                 end
202                 `DECODE_CDP:            /* Coprocessor data op */
203                 begin
204                 end
205                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
206                 begin
207                         read_0 = insn[15:12];
208                         
209                         op0_out = regs0;
210                 end
211                 `DECODE_SWI:            /* SWI */
212                 begin
213                 end
214                 default:
215                         $display("Undecoded instruction");
216                 endcase
217         end
218
219         
220         always @ (posedge clk) begin
221                 op0 <= op0_out;   /* Rn - always */
222                 op1 <= op1_out; /* 'operand 2' - Rm */
223                 op2 <= op2_out;   /* thirdedge - Rs */
224                 carry <= carry_out;
225                 outspsr <= inspsr;
226         end
227
228 endmodule
229
230 module IREALLYHATEARMSHIFT(
231         input [31:0] insn,
232         input [31:0] operand,
233         input [31:0] reg_amt,
234         input cflag_in,
235         output reg [31:0] res,
236         output reg cflag_out
237 );
238         wire [5:0] shift_amt;
239         reg is_arith, is_rot;
240         wire rshift_cout;
241         wire [31:0] rshift_res;
242
243         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
244                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
245
246         SuckLessShifter barrel(.oper(operand),
247                                .carryin(cflag_in),
248                                .amt(shift_amt),
249                                .is_arith(is_arith),
250                                .is_rot(is_rot),
251                                .res(rshift_res),
252                                .carryout(rshift_cout));
253
254         always @(*)
255                 case (insn[6:5])
256                 `SHIFT_LSL: begin
257                         /* meaningless */
258                         is_rot = 1'b0;
259                         is_arith = 1'b0;
260                 end
261                 `SHIFT_LSR: begin
262                         is_rot = 1'b0;
263                         is_arith = 1'b0;
264                 end
265                 `SHIFT_ASR: begin
266                         is_rot = 1'b0;
267                         is_arith = 1'b1;
268                 end
269                 `SHIFT_ROR: begin
270                         is_rot = 1'b1;
271                         is_arith = 1'b0;
272                 end
273                 endcase
274
275         always @(*)
276                 case (insn[6:5]) /* shift type */
277                 `SHIFT_LSL:
278                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
279                 `SHIFT_LSR: begin
280                         res = rshift_res;
281                         cflag_out = rshift_cout;
282                 end
283                 `SHIFT_ASR: begin
284                         res = rshift_res;
285                         cflag_out = rshift_cout;
286                 end
287                 `SHIFT_ROR: begin
288                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
289                                 res = {cflag_in, operand[31:1]};
290                                 cflag_out = operand[0];
291                         end else begin
292                                 res = rshift_res;
293                                 cflag_out = rshift_cout;
294                         end
295                 end
296                 endcase
297 endmodule
298
299 module SuckLessShifter(
300         input [31:0] oper,
301         input carryin,
302         input [5:0] amt,
303         input is_arith,
304         input is_rot,
305         output wire [31:0] res,
306         output wire carryout
307 );
308
309         wire [32:0] stage1, stage2, stage3, stage4, stage5;
310
311         wire pushbits = is_arith & oper[31];
312
313         /* do a barrel shift */
314         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
315         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
316         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
317         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
318         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
319         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
320
321 endmodule
322
323 module SuckLessRotator(
324         input [31:0] oper,
325         input [3:0] amt,
326         output wire [31:0] res
327 );
328
329         wire [31:0] stage1, stage2, stage3;
330         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
331         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
332         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
333         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
334
335 endmodule
336
This page took 0.036482 seconds and 4 git commands to generate.