Decode.v

   1 `include "ARM_Constants.v"
   2
   3 module Decode(
   4         input clk,
   5         input [31:0] insn,
   6         input [31:0] inpc,
   7         input [31:0] incpsr,
   8         input [31:0] inspsr,
   9         output reg [31:0] op0,
  10         output reg [31:0] op1,
  11         output reg [31:0] op2,
  12         output reg carry,
  13         output reg [31:0] outcpsr,
  14         output reg [31:0] outspsr,
  15
  16         output reg [3:0] read_0,
  17         output reg [3:0] read_1,
  18         output reg [3:0] read_2,
  19         input [31:0] rdata_0,
  20         input [31:0] rdata_1,
  21         input [31:0] rdata_2
  22         );
  23
  24         wire [31:0] regs0, regs1, regs2;
  25         reg [31:0] rpc;
  26         reg [31:0] op0_out, op1_out, op2_out;
  27         reg carry_out;
  28
  29         /* shifter stuff */
  30         wire [31:0] shift_oper;
  31         wire [31:0] shift_res;
  32         wire shift_cflag_out;
  33         wire [31:0] rotate_res;
  34
  35         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
  36         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
  37         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
  38
  39         IREALLYHATEARMSHIFT shift(.insn(insn),
  40                                   .operand(regs1),
  41                                   .reg_amt(regs2),
  42                                   .cflag_in(incpsr[`CPSR_C]),
  43                                   .res(shift_res),
  44                                   .cflag_out(shift_cflag_out));
  45
  46         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
  47                               .amt(insn[11:8]),
  48                               .res(rotate_res));
  49
  50         always @(*)
  51                 casez (insn)
  52                 `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  53 //              `DECODE_ALU_MUL_LONG,           /* Multiply long */
  54                 `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
  55                 `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
  56                 `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
  57                 `DECODE_ALU_SWP,                /* Atomic swap */
  58                 `DECODE_ALU_BX,                 /* Branch and exchange */
  59                 `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
  60                 `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
  61                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
  62                 `DECODE_LDRSTR,                 /* Single data transfer */
  63                 `DECODE_LDMSTM,                 /* Block data transfer */
  64                 `DECODE_BRANCH,                 /* Branch */
  65                 `DECODE_LDCSTC,                 /* Coprocessor data transfer */
  66                 `DECODE_CDP,                    /* Coprocessor data op */
  67                 `DECODE_SWI:                    /* SWI */
  68                         rpc = inpc + 8;
  69                 `DECODE_MRCMCR:                 /* Coprocessor register transfer */
  70                         rpc = inpc + 12;
  71                 `DECODE_ALU:                    /* ALU */
  72                         rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
  73                 default:                        /* X everything else out */
  74                         rpc = 32'hxxxxxxxx;
  75                 endcase
  76
  77         always @(*) begin
  78                 read_0 = 4'hx;
  79                 read_1 = 4'hx;
  80                 read_2 = 4'hx;
  81
  82                 op0_out = 32'hxxxxxxxx;
  83                 op1_out = 32'hxxxxxxxx;
  84                 op2_out = 32'hxxxxxxxx;
  85                 carry_out = 1'bx;
  86
  87                 casez (insn)
  88                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  89                 begin
  90                         read_0 = insn[15:12]; /* Rn */
  91                         read_1 = insn[3:0];   /* Rm */
  92                         read_2 = insn[11:8];  /* Rs */
  93
  94                         op0_out = regs0;
  95                         op1_out = regs1;
  96                         op2_out = regs2;
  97                 end
  98 //              `DECODE_ALU_MUL_LONG:   /* Multiply long */
  99 //              begin
 100 //                      read_0 = insn[11:8]; /* Rn */
 101 //                      read_1 = insn[3:0];   /* Rm */
 102 //                      read_2 = 4'b0;       /* anyus */
 103 //
 104 //                      op1_res = regs1;
 105 //              end
 106                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
 107                 begin end
 108                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
 109                 begin
 110                         read_0 = insn[3:0];     /* Rm */
 111
 112                         op0_out = regs0;
 113                 end
 114                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 115                 begin
 116                         read_0 = insn[3:0];     /* Rm */
 117
 118                         if(insn[25]) begin     /* the constant case */
 119                                 op0_out = rotate_res;
 120                         end else begin
 121                                 op0_out = regs0;
 122                         end
 123                 end
 124                 `DECODE_ALU_SWP:        /* Atomic swap */
 125                 begin
 126                         read_0 = insn[19:16]; /* Rn */
 127                         read_1 = insn[3:0];   /* Rm */
 128
 129                         op0_out = regs0;
 130                         op1_out = regs1;
 131                 end
 132                 `DECODE_ALU_BX:         /* Branch and exchange */
 133                 begin
 134                         read_0 = insn[3:0];   /* Rn */
 135
 136                         op0_out = regs0;
 137                 end
 138                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
 139                 begin
 140                         read_0 = insn[19:16];
 141                         read_1 = insn[3:0];
 142
 143                         op0_out = regs0;
 144                         op1_out = regs1;
 145                 end
 146                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 147                 begin
 148                         read_0 = insn[19:16];
 149
 150                         op0_out = regs0;
 151                         op1_out = {24'b0, insn[11:8], insn[3:0]};
 152                 end
 153                 `DECODE_ALU:            /* ALU */
 154                 begin
 155                         read_0 = insn[19:16]; /* Rn */
 156                         read_1 = insn[3:0];   /* Rm */
 157                         read_2 = insn[11:8];  /* Rs for shift */
 158
 159                         op0_out = regs0;
 160                         if(insn[25]) begin     /* the constant case */
 161                                 carry_out = incpsr[`CPSR_C];
 162                                 op1_out = rotate_res;
 163                         end else begin
 164                                 carry_out = shift_cflag_out;
 165                                 op1_out = shift_res;
 166                         end
 167                 end
 168                 `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
 169                 begin
 170                         /* eat shit */
 171                 end
 172                 `DECODE_LDRSTR:         /* Single data transfer */
 173                 begin
 174                         read_0 = insn[19:16]; /* Rn */
 175                         read_1 = insn[3:0];   /* Rm */
 176                         read_2 = insn[15:12];
 177
 178                         op0_out = regs0;
 179                         if(insn[25]) begin
 180                                 op1_out = {20'b0, insn[11:0]};
 181                                 carry_out = incpsr[`CPSR_C];
 182                         end else begin
 183                                 op1_out = shift_res;
 184                                 carry_out = shift_cflag_out;
 185                         end
 186                         op2_out = regs2;
 187                 end
 188                 `DECODE_LDMSTM:         /* Block data transfer */
 189                 begin
 190                         read_0 = insn[19:16];
 191
 192                         op0_out = regs0;
 193                         op1_out = {16'b0, insn[15:0]};
 194                 end
 195                 `DECODE_BRANCH:         /* Branch */
 196                 begin
 197                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
 198                 end
 199                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
 200                 begin
 201                         read_0 = insn[19:16];
 202
 203                         op0_out = regs0;
 204                         op1_out = {24'b0, insn[7:0]};
 205                 end
 206                 `DECODE_CDP:            /* Coprocessor data op */
 207                 begin
 208                 end
 209                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
 210                 begin
 211                         read_0 = insn[15:12];
 212
 213                         op0_out = regs0;
 214                 end
 215                 `DECODE_SWI:            /* SWI */
 216                 begin
 217                 end
 218                 default:
 219                         $display("Undecoded instruction");
 220                 endcase
 221         end
 222
 223
 224         always @ (posedge clk) begin
 225                 op0 <= op0_out;   /* Rn - always */
 226                 op1 <= op1_out; /* 'operand 2' - Rm */
 227                 op2 <= op2_out;   /* thirdedge - Rs */
 228                 carry <= carry_out;
 229                 outcpsr <= incpsr;
 230                 outspsr <= inspsr;
 231         end
 232
 233 endmodule
 234
 235 module IREALLYHATEARMSHIFT(
 236         input [31:0] insn,
 237         input [31:0] operand,
 238         input [31:0] reg_amt,
 239         input cflag_in,
 240         output reg [31:0] res,
 241         output reg cflag_out
 242 );
 243         wire [5:0] shift_amt;
 244         reg is_arith, is_rot;
 245         wire rshift_cout;
 246         wire [31:0] rshift_res;
 247
 248         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
 249                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
 250
 251         SuckLessShifter barrel(.oper(operand),
 252                                .carryin(cflag_in),
 253                                .amt(shift_amt),
 254                                .is_arith(is_arith),
 255                                .is_rot(is_rot),
 256                                .res(rshift_res),
 257                                .carryout(rshift_cout));
 258
 259         always @(*)
 260                 case (insn[6:5])
 261                 `SHIFT_LSL: begin
 262                         /* meaningless */
 263                         is_rot = 1'b0;
 264                         is_arith = 1'b0;
 265                 end
 266                 `SHIFT_LSR: begin
 267                         is_rot = 1'b0;
 268                         is_arith = 1'b0;
 269                 end
 270                 `SHIFT_ASR: begin
 271                         is_rot = 1'b0;
 272                         is_arith = 1'b1;
 273                 end
 274                 `SHIFT_ROR: begin
 275                         is_rot = 1'b1;
 276                         is_arith = 1'b0;
 277                 end
 278                 endcase
 279
 280         always @(*)
 281                 case (insn[6:5]) /* shift type */
 282                 `SHIFT_LSL:
 283                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
 284                 `SHIFT_LSR: begin
 285                         res = rshift_res;
 286                         cflag_out = rshift_cout;
 287                 end
 288                 `SHIFT_ASR: begin
 289                         res = rshift_res;
 290                         cflag_out = rshift_cout;
 291                 end
 292                 `SHIFT_ROR: begin
 293                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
 294                                 res = {cflag_in, operand[31:1]};
 295                                 cflag_out = operand[0];
 296                         end else begin
 297                                 res = rshift_res;
 298                                 cflag_out = rshift_cout;
 299                         end
 300                 end
 301                 endcase
 302 endmodule
 303
 304 module SuckLessShifter(
 305         input [31:0] oper,
 306         input carryin,
 307         input [5:0] amt,
 308         input is_arith,
 309         input is_rot,
 310         output wire [31:0] res,
 311         output wire carryout
 312 );
 313
 314         wire [32:0] stage1, stage2, stage3, stage4, stage5;
 315
 316         wire pushbits = is_arith & oper[31];
 317
 318         /* do a barrel shift */
 319         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
 320         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
 321         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
 322         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
 323         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
 324         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
 325
 326 endmodule
 327
 328 module SuckLessRotator(
 329         input [31:0] oper,
 330         input [3:0] amt,
 331         output wire [31:0] res
 332 );
 333
 334         wire [31:0] stage1, stage2, stage3;
 335         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
 336         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
 337         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
 338         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
 339
 340 endmodule
 341