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Regfile: Rename signals for correct pipe stages.
[firearm.git] / xst / impact.cmd
1 setMode -bs
2 setCable -port svf -file "XXX.svf"
3 addDevice -p 1 -file "XXX.bit"
4 addDevice -p 2 -part xcf04s
5 Program -p 1 -defaultVersion 0
6 quit
7
FireARM pipelined ARM-like CPU implementation in Verilog
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