DCache: I/O rename
[firearm.git] / RegFile.v
... / ...
CommitLineData
1module RegFile(
2 input clk,
3 input Nrst,
4 input [3:0] rf__read_0_1a,
5 output wire [31:0] rf__rdata_0_1a,
6 input [3:0] rf__read_1_1a,
7 output wire [31:0] rf__rdata_1_1a,
8 input [3:0] rf__read_2_1a,
9 output wire [31:0] rf__rdata_2_1a,
10 input [3:0] rf__read_3_4a,
11 output wire [31:0] rf__rdata_3_4a,
12 output wire [31:0] spsr,
13 input write,
14 input [3:0] write_reg,
15 input [31:0] write_data
16 );
17
18 reg [31:0] regfile [0:15];
19 integer i;
20
21 initial begin
22 for (i = 0; i < 16; i = i + 1)
23 regfile[i] = 0;
24 end
25
26 assign rf__rdata_0_1a = ((rf__read_0_1a == write_reg) && write) ? write_data : regfile[rf__read_0_1a];
27 assign rf__rdata_1_1a = ((rf__read_1_1a == write_reg) && write) ? write_data : regfile[rf__read_1_1a];
28 assign rf__rdata_2_1a = ((rf__read_2_1a == write_reg) && write) ? write_data : regfile[rf__read_2_1a];
29 assign rf__rdata_3_4a = ((rf__read_3_4a == write_reg) && write) ? write_data : regfile[rf__read_3_4a];
30 assign spsr = regfile[4'hF];
31
32 always @(posedge clk or negedge Nrst)
33 if (!Nrst) begin
34 for (i = 0; i < 16; i = i + 1)
35 regfile[i] <= 0;
36 end else if (write)
37 regfile[write_reg] <= write_data;
38endmodule
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