Issue: Add logic to defer a flush if need be (i.e., we're stalled at the time and...
[firearm.git] / Memory.v
... / ...
CommitLineData
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
6
7 input flush,
8
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
16 output reg [2:0] data_size,
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
21
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
29
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
34 input [31:0] op0,
35 input [31:0] op1,
36 input [31:0] op2,
37 input [31:0] spsr,
38 input [31:0] cpsr,
39 input write_reg,
40 input [3:0] write_num,
41 input [31:0] write_data,
42
43 /* outputs */
44 output reg outstall,
45 output reg outbubble,
46 output reg [31:0] outpc,
47 output reg [31:0] outinsn,
48 output reg out_write_reg = 1'b0,
49 output reg [3:0] out_write_num = 4'bxxxx,
50 output reg [31:0] out_write_data = 32'hxxxxxxxx,
51 output reg [31:0] outspsr = 32'hxxxxxxxx,
52 output reg [31:0] outcpsr = 32'hxxxxxxxx
53 );
54
55 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
56 reg [31:0] prevaddr;
57 reg [3:0] next_regsel, cur_reg, prev_reg;
58 reg next_writeback;
59
60 reg next_outbubble;
61 reg next_write_reg;
62 reg [3:0] next_write_num;
63 reg [31:0] next_write_data;
64
65 reg [1:0] lsr_state = 2'b01, next_lsr_state;
66 reg [31:0] align_s1, align_s2, align_rddata;
67
68 reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
69 reg [31:0] lsrh_rddata;
70 reg [15:0] lsrh_rddata_s1;
71 reg [7:0] lsrh_rddata_s2;
72
73 reg [15:0] regs, next_regs;
74 reg [2:0] lsm_state = 3'b001, next_lsm_state;
75 reg [5:0] offset, prev_offset, offset_sel;
76
77 reg [31:0] swp_oldval, next_swp_oldval;
78 reg [1:0] swp_state = 2'b01, next_swp_state;
79
80 always @(posedge clk)
81 begin
82 outpc <= pc;
83 outinsn <= insn;
84 outbubble <= next_outbubble;
85 out_write_reg <= next_write_reg;
86 out_write_num <= next_write_num;
87 out_write_data <= next_write_data;
88 regs <= next_regs;
89 prev_reg <= cur_reg;
90 prev_offset <= offset;
91 prev_raddr <= raddr;
92 outcpsr <= next_outcpsr;
93 outspsr <= spsr;
94 swp_state <= next_swp_state;
95 lsm_state <= next_lsm_state;
96 lsr_state <= next_lsr_state;
97 lsrh_state <= next_lsrh_state;
98 prevaddr <= addr;
99 end
100
101 always @(*)
102 begin
103 addr = prevaddr;
104 raddr = 32'hxxxxxxxx;
105 rd_req = 1'b0;
106 wr_req = 1'b0;
107 wr_data = 32'hxxxxxxxx;
108 busaddr = 32'hxxxxxxxx;
109 data_size = 3'bxxx;
110 outstall = 1'b0;
111 next_write_reg = write_reg;
112 next_write_num = write_num;
113 next_write_data = write_data;
114 next_outbubble = inbubble;
115 next_regs = regs;
116 cp_req = 1'b0;
117 cp_rnw = 1'bx;
118 cp_write = 32'hxxxxxxxx;
119 offset = prev_offset;
120 next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
121 lsrh_rddata = 32'hxxxxxxxx;
122 lsrh_rddata_s1 = 16'hxxxx;
123 lsrh_rddata_s2 = 8'hxx;
124 next_lsm_state = lsm_state;
125 next_lsr_state = lsr_state;
126 next_lsrh_state = lsrh_state;
127 next_swp_oldval = swp_oldval;
128 next_swp_state = swp_state;
129 cur_reg = prev_reg;
130
131 /* XXX shit not given about endianness */
132 if (flush)
133 next_outbubble = 1'b1;
134 else casez(insn)
135 `DECODE_ALU_SWP: if(!inbubble) begin
136 outstall = rw_wait;
137 next_outbubble = rw_wait;
138 busaddr = {op0[31:2], 2'b0};
139 data_size = insn[22] ? 3'b001 : 3'b100;
140 case(swp_state)
141 2'b01: begin
142 rd_req = 1'b1;
143 outstall = 1'b1;
144 if(!rw_wait) begin
145 next_swp_state = 2'b10;
146 next_swp_oldval = rd_data;
147 end
148 end
149 2'b10: begin
150 wr_req = 1'b1;
151 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
152 next_write_reg = 1'b1;
153 next_write_num = insn[15:12];
154 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
155 if(!rw_wait)
156 next_swp_state = 2'b01;
157 end
158 default: begin end
159 endcase
160 end
161 `DECODE_ALU_HDATA_REG,
162 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
163 next_outbubble = rw_wait;
164 outstall = rw_wait;
165 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
166 raddr = insn[24] ? op0 : addr; /* pre/post increment */
167 busaddr = raddr;
168 /* rotate to correct position */
169 case(insn[6:5])
170 2'b00: begin end /* swp */
171 2'b01: begin /* unsigned half */
172 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
173 data_size = 3'b010;
174 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
175 end
176 2'b10: begin /* signed byte */
177 wr_data = {4{op2[7:0]}};
178 data_size = 3'b001;
179 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
180 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
181 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
182 end
183 2'b11: begin /* signed half */
184 wr_data = {2{op2[15:0]}};
185 data_size = 3'b010;
186 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
187 end
188 endcase
189
190 case(lsrh_state)
191 2'b01: begin
192 rd_req = insn[20];
193 wr_req = ~insn[20];
194 next_write_num = insn[15:12];
195 next_write_data = lsrh_rddata;
196 if(insn[20]) begin
197 next_write_reg = 1'b1;
198 end
199 if(insn[21] | !insn[24]) begin
200 outstall = 1'b1;
201 if(!rw_wait)
202 next_lsrh_state = 2'b10;
203 end
204 end
205 2'b10: begin
206 next_write_reg = 1'b1;
207 next_write_num = insn[19:16];
208 next_write_data = addr;
209 next_lsrh_state = 2'b10;
210 end
211 default: begin end
212 endcase
213 end
214 `DECODE_LDRSTR_UNDEFINED: begin end
215 `DECODE_LDRSTR: if(!inbubble) begin
216 next_outbubble = rw_wait;
217 outstall = rw_wait;
218 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
219 raddr = insn[24] ? addr : op0; /* pre/post increment */
220 busaddr = raddr;
221 /* rotate to correct position */
222 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
223 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
224 /* select byte or word */
225 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
226 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
227 data_size = insn[22] ? 3'b001 : 3'b100;
228 case(lsr_state)
229 2'b01: begin
230 rd_req = insn[20];
231 wr_req = ~insn[20];
232 next_write_reg = 1'b1;
233 next_write_num = insn[15:12];
234 if(insn[20]) begin
235 next_write_data = align_rddata;
236 end
237 if(insn[21] | !insn[24]) begin
238 outstall = 1'b1;
239 if(!rw_wait)
240 next_lsr_state = 2'b10;
241 end
242 end
243 2'b10: begin
244 next_write_reg = 1'b1;
245 next_write_num = insn[19:16];
246 next_write_data = addr;
247 next_lsr_state = 2'b01;
248 end
249 default: begin end
250 endcase
251 end
252 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
253 `DECODE_LDMSTM: if(!inbubble) begin
254 outstall = rw_wait;
255 next_outbubble = rw_wait;
256 data_size = 3'b100;
257 case(lsm_state)
258 3'b001: begin
259// next_regs = insn[23] ? op1[15:0] : op1[0:15];
260 /** verilator can suck my dick */
261 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
262 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
263 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
264 offset = 6'b0;
265 outstall = 1'b1;
266 next_lsm_state = 3'b010;
267 end
268 3'b010: begin
269 rd_req = insn[20];
270 wr_req = ~insn[20];
271 casez(regs)
272 16'b???????????????1: begin
273 cur_reg = 4'h0;
274 next_regs = {regs[15:1], 1'b0};
275 end
276 16'b??????????????10: begin
277 cur_reg = 4'h1;
278 next_regs = {regs[15:2], 2'b0};
279 end
280 16'b?????????????100: begin
281 cur_reg = 4'h2;
282 next_regs = {regs[15:3], 3'b0};
283 end
284 16'b????????????1000: begin
285 cur_reg = 4'h3;
286 next_regs = {regs[15:4], 4'b0};
287 end
288 16'b???????????10000: begin
289 cur_reg = 4'h4;
290 next_regs = {regs[15:5], 5'b0};
291 end
292 16'b??????????100000: begin
293 cur_reg = 4'h5;
294 next_regs = {regs[15:6], 6'b0};
295 end
296 16'b?????????1000000: begin
297 cur_reg = 4'h6;
298 next_regs = {regs[15:7], 7'b0};
299 end
300 16'b????????10000000: begin
301 cur_reg = 4'h7;
302 next_regs = {regs[15:8], 8'b0};
303 end
304 16'b???????100000000: begin
305 cur_reg = 4'h8;
306 next_regs = {regs[15:9], 9'b0};
307 end
308 16'b??????1000000000: begin
309 cur_reg = 4'h9;
310 next_regs = {regs[15:10], 10'b0};
311 end
312 16'b?????10000000000: begin
313 cur_reg = 4'hA;
314 next_regs = {regs[15:11], 11'b0};
315 end
316 16'b????100000000000: begin
317 cur_reg = 4'hB;
318 next_regs = {regs[15:12], 12'b0};
319 end
320 16'b???1000000000000: begin
321 cur_reg = 4'hC;
322 next_regs = {regs[15:13], 13'b0};
323 end
324 16'b??10000000000000: begin
325 cur_reg = 4'hD;
326 next_regs = {regs[15:14], 14'b0};
327 end
328 16'b?100000000000000: begin
329 cur_reg = 4'hE;
330 next_regs = {regs[15], 15'b0};
331 end
332 16'b1000000000000000: begin
333 cur_reg = 4'hF;
334 next_regs = 16'b0;
335 end
336 default: begin
337 cur_reg = 4'hx;
338 next_regs = 16'b0;
339 end
340 endcase
341 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
342 if(cur_reg == 4'hF && insn[22]) begin
343 next_outcpsr = spsr;
344 end
345
346 if(rw_wait) begin
347 next_regs = regs;
348 cur_reg = prev_reg;
349 raddr = prev_raddr;
350 end
351 else begin
352 offset = prev_offset + 6'h4;
353 offset_sel = insn[24] ? offset : prev_offset;
354 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
355 if(insn[20]) begin
356 next_write_reg = 1'b1;
357 next_write_num = cur_reg;
358 next_write_data = rd_data;
359 end
360 end
361
362 st_read = cur_reg;
363 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
364 busaddr = raddr;
365
366 $display("LDMSTM: Stage 2: Writing: reg %d, wr_data %08x, addr %08x", cur_reg, wr_data, busaddr);
367
368 outstall = 1'b1;
369
370 if(next_regs == 16'b0) begin
371 next_lsm_state = 3'b100;
372 end
373 end
374 3'b100: begin
375 next_write_reg = insn[21] /* writeback */;
376 next_write_num = insn[19:16];
377 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
378 next_lsm_state = 3'b001;
379 end
380 default: begin end
381 endcase
382 end
383 `DECODE_LDCSTC: if(!inbubble) begin
384 $display("WARNING: Unimplemented LDCSTC");
385 end
386 `DECODE_CDP: if(!inbubble) begin
387 cp_req = 1;
388 if (cp_busy) begin
389 outstall = 1;
390 next_outbubble = 1;
391 end
392 if (!cp_ack) begin
393 /* XXX undefined instruction trap */
394 $display("WARNING: Possible CDP undefined instruction");
395 end
396 end
397 `DECODE_MRCMCR: if(!inbubble) begin
398 cp_req = 1;
399 cp_rnw = insn[20] /* L */;
400 if (insn[20] == 0 /* store to coprocessor */)
401 cp_write = op0;
402 else begin
403 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
404 next_write_reg = 1'b1;
405 next_write_num = insn[15:12];
406 next_write_data = cp_read;
407 end else
408 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
409 end
410 if (cp_busy) begin
411 outstall = 1;
412 next_outbubble = 1;
413 end
414 if (!cp_ack) begin
415 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
416 end
417 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
418 end
419 default: begin end
420 endcase
421 end
422endmodule
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