Costas: Remove while(1) and allow proper returns.
[firearm.git] / system.v
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CommitLineData
1`define BUS_ICACHE 0
2`define BUS_DCACHE 1
3
4module System(input clk);
5 wire [7:0] bus_req;
6 wire [7:0] bus_ack;
7 wire [31:0] bus_addr;
8 wire [31:0] bus_rdata;
9 wire [31:0] bus_wdata;
10 wire bus_rd, bus_wr;
11 wire bus_ready;
12
13 wire bus_req_icache;
14 wire bus_req_dcache;
15 assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
16 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
17 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
18
19 wire [31:0] bus_addr_icache;
20 wire [31:0] bus_wdata_icache;
21 wire bus_rd_icache;
22 wire bus_wr_icache;
23
24 wire [31:0] bus_addr_dcache;
25 wire [31:0] bus_wdata_dcache;
26 wire bus_rd_dcache;
27 wire bus_wr_dcache;
28
29 wire [31:0] bus_rdata_blockram;
30 wire bus_ready_blockram;
31
32 assign bus_addr = bus_addr_icache | bus_addr_dcache;
33 assign bus_rdata = bus_rdata_blockram;
34 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
35 assign bus_rd = bus_rd_icache | bus_rd_dcache;
36 assign bus_wr = bus_wr_icache | bus_wr_dcache;
37 assign bus_ready = bus_ready_blockram;
38
39 wire [31:0] icache_rd_addr;
40 wire icache_rd_req;
41 wire icache_rd_wait;
42 wire [31:0] icache_rd_data;
43
44 wire [31:0] dcache_addr;
45 wire dcache_rd_req, dcache_wr_req;
46 wire dcache_rw_wait;
47 wire [31:0] dcache_wr_data, dcache_rd_data;
48
49 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
50 wire decode_out_carry;
51
52 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
53 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
54 wire regfile_write;
55 wire [3:0] regfile_write_reg;
56 wire [31:0] regfile_write_data;
57
58 wire execute_out_write_reg;
59 wire [3:0] execute_out_write_num;
60 wire [31:0] execute_out_write_data;
61 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
62 wire [31:0] execute_out_cpsr, execute_out_spsr;
63
64 wire jmp_out_execute, jmp_out_writeback;
65 wire [31:0] jmppc_out_execute, jmppc_out_writeback;
66 wire jmp = jmp_out_execute | jmp_out_writeback;
67 wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
68
69 wire memory_out_write_reg;
70 wire [3:0] memory_out_write_num;
71 wire [31:0] memory_out_write_data;
72 wire [31:0] memory_out_cpsr, memory_out_spsr;
73
74 wire [31:0] writeback_out_cpsr, writeback_out_spsr;
75
76 wire cp_ack_terminal;
77 wire cp_busy_terminal;
78 wire [31:0] cp_read_terminal;
79
80 wire cp_req;
81 wire [31:0] cp_insn;
82 wire cp_ack = cp_ack_terminal;
83 wire cp_busy = cp_busy_terminal;
84 wire cp_rnw;
85 wire [31:0] cp_read = cp_read_terminal;
86 wire [31:0] cp_write;
87
88 wire stall_cause_issue;
89 wire stall_cause_execute;
90 wire stall_cause_memory;
91 wire bubble_out_fetch;
92 wire bubble_out_issue;
93 wire bubble_out_execute;
94 wire bubble_out_memory;
95 wire [31:0] insn_out_fetch;
96 wire [31:0] insn_out_issue;
97 wire [31:0] insn_out_execute;
98 wire [31:0] insn_out_memory;
99 wire [31:0] pc_out_fetch;
100 wire [31:0] pc_out_issue;
101 wire [31:0] pc_out_execute;
102 wire [31:0] pc_out_memory;
103
104 wire execute_out_backflush;
105 wire writeback_out_backflush;
106
107 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
108
109 ICache icache(
110 .clk(clk),
111 /* XXX reset? */
112 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
113 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
114 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
115 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
116 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
117 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
118
119 DCache dcache(
120 .clk(clk),
121 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
122 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
123 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
124 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
125 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
126 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
127
128 BlockRAM blockram(
129 .clk(clk),
130 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
131 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
132 .bus_ready(bus_ready_blockram));
133
134 Fetch fetch(
135 .clk(clk),
136 .Nrst(1'b1 /* XXX */),
137 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
138 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
139 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
140 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
141 .pc(pc_out_fetch));
142
143 Issue issue(
144 .clk(clk),
145 .Nrst(1'b1 /* XXX */),
146 .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
147 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
148 .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
149 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
150 .outpc(pc_out_issue), .outinsn(insn_out_issue));
151
152 RegFile regfile(
153 .clk(clk),
154 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
155 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
156 .spsr(regfile_spsr),
157 .write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
158
159 Decode decode(
160 .clk(clk),
161 .stall(stall_cause_execute),
162 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
163 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
164 .carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
165 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
166 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
167
168 Execute execute(
169 .clk(clk), .Nrst(1'b0),
170 .stall(stall_cause_memory), .flush(writeback_out_backflush),
171 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
172 .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
173 .op2(decode_out_op2), .carry(decode_out_carry),
174 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
175 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
176 .write_data(execute_out_write_data),
177 .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
178 .outpc(pc_out_execute), .outinsn(insn_out_execute),
179 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
180 .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
181 assign execute_out_backflush = jmp;
182
183 assign cp_insn = insn_out_execute;
184 Memory memory(
185 .clk(clk), .Nrst(1'b0),
186 /* stall? */ .flush(writeback_out_backflush),
187 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
188 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
189 .st_read(regfile_read_3), .st_data(regfile_rdata_3),
190 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
191 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
192 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr),
193 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
194 .outstall(stall_cause_memory), .outbubble(bubble_out_memory),
195 .outpc(pc_out_memory), .outinsn(insn_out_memory),
196 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
197 .out_write_data(memory_out_write_data),
198 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
199 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr) /* XXX data_size */);
200
201 Terminal terminal(
202 .clk(clk),
203 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
204 .cp_read(cp_read_terminal), .cp_write(cp_write));
205
206 Writeback writeback(
207 .clk(clk),
208 .inbubble(bubble_out_memory),
209 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
210 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr),
211 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
212 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
213 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
214 assign writeback_out_backflush = jmp_out_writeback;
215
216 reg [31:0] clockno = 0;
217 always @(posedge clk)
218 begin
219 clockno <= clockno + 1;
220 $display("------------------------------------------------------------------------------");
221 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
222 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
223 $display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
224 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
225 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
226 $display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
227 end
228endmodule
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