| 1 | `include "ARM_Constants.v" |
| 2 | |
| 3 | module Decode( |
| 4 | input clk, |
| 5 | input [31:0] insn, |
| 6 | input [31:0] inpc, |
| 7 | input [31:0] incpsr, |
| 8 | input [31:0] inspsr, |
| 9 | output reg [31:0] op0, |
| 10 | output reg [31:0] op1, |
| 11 | output reg [31:0] op2, |
| 12 | output reg carry, |
| 13 | output reg [31:0] outspsr, |
| 14 | |
| 15 | output reg [3:0] read_0, |
| 16 | output reg [3:0] read_1, |
| 17 | output reg [3:0] read_2, |
| 18 | input [31:0] rdata_0, |
| 19 | input [31:0] rdata_1, |
| 20 | input [31:0] rdata_2 |
| 21 | ); |
| 22 | |
| 23 | wire [31:0] regs0, regs1, regs2; |
| 24 | reg [31:0] rpc; |
| 25 | reg [31:0] op0_out, op1_out, op2_out; |
| 26 | reg carry_out; |
| 27 | |
| 28 | /* shifter stuff */ |
| 29 | wire [31:0] shift_oper; |
| 30 | wire [31:0] shift_res; |
| 31 | wire shift_cflag_out; |
| 32 | wire [31:0] rotate_res; |
| 33 | |
| 34 | assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0; |
| 35 | assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1; |
| 36 | assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */ |
| 37 | |
| 38 | IREALLYHATEARMSHIFT shift(.insn(insn), |
| 39 | .operand(regs1), |
| 40 | .reg_amt(regs2), |
| 41 | .cflag_in(incpsr[`CPSR_C]), |
| 42 | .res(shift_res), |
| 43 | .cflag_out(shift_cflag_out)); |
| 44 | |
| 45 | SuckLessRotator whirr(.oper({24'b0, insn[7:0]}), |
| 46 | .amt(insn[11:8]), |
| 47 | .res(rotate_res)); |
| 48 | |
| 49 | always @(*) |
| 50 | casez (insn) |
| 51 | `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ |
| 52 | // `DECODE_ALU_MUL_LONG, /* Multiply long */ |
| 53 | `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */ |
| 54 | `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */ |
| 55 | `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */ |
| 56 | `DECODE_ALU_SWP, /* Atomic swap */ |
| 57 | `DECODE_ALU_BX, /* Branch and exchange */ |
| 58 | `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */ |
| 59 | `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */ |
| 60 | `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */ |
| 61 | `DECODE_LDRSTR, /* Single data transfer */ |
| 62 | `DECODE_LDMSTM, /* Block data transfer */ |
| 63 | `DECODE_BRANCH, /* Branch */ |
| 64 | `DECODE_LDCSTC, /* Coprocessor data transfer */ |
| 65 | `DECODE_CDP, /* Coprocessor data op */ |
| 66 | `DECODE_SWI: /* SWI */ |
| 67 | rpc = inpc + 8; |
| 68 | `DECODE_MRCMCR: /* Coprocessor register transfer */ |
| 69 | rpc = inpc + 12; |
| 70 | `DECODE_ALU: /* ALU */ |
| 71 | rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8)); |
| 72 | default: /* X everything else out */ |
| 73 | rpc = 32'hxxxxxxxx; |
| 74 | endcase |
| 75 | |
| 76 | always @(*) begin |
| 77 | read_0 = 4'hx; |
| 78 | read_1 = 4'hx; |
| 79 | read_2 = 4'hx; |
| 80 | |
| 81 | op0_out = 32'hxxxxxxxx; |
| 82 | op1_out = 32'hxxxxxxxx; |
| 83 | op2_out = 32'hxxxxxxxx; |
| 84 | carry_out = 1'bx; |
| 85 | |
| 86 | casez (insn) |
| 87 | `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ |
| 88 | begin |
| 89 | read_0 = insn[15:12]; /* Rn */ |
| 90 | read_1 = insn[3:0]; /* Rm */ |
| 91 | read_2 = insn[11:8]; /* Rs */ |
| 92 | |
| 93 | op0_out = regs0; |
| 94 | op1_out = regs1; |
| 95 | op2_out = regs2; |
| 96 | end |
| 97 | // `DECODE_ALU_MUL_LONG: /* Multiply long */ |
| 98 | // begin |
| 99 | // read_0 = insn[11:8]; /* Rn */ |
| 100 | // read_1 = insn[3:0]; /* Rm */ |
| 101 | // read_2 = 4'b0; /* anyus */ |
| 102 | // |
| 103 | // op1_res = regs1; |
| 104 | // end |
| 105 | `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */ |
| 106 | begin end |
| 107 | `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */ |
| 108 | begin |
| 109 | read_0 = insn[3:0]; /* Rm */ |
| 110 | |
| 111 | op0_out = regs0; |
| 112 | end |
| 113 | `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */ |
| 114 | begin |
| 115 | read_0 = insn[3:0]; /* Rm */ |
| 116 | |
| 117 | if(insn[25]) begin /* the constant case */ |
| 118 | op0_out = rotate_res; |
| 119 | end else begin |
| 120 | op0_out = regs0; |
| 121 | end |
| 122 | end |
| 123 | `DECODE_ALU_SWP: /* Atomic swap */ |
| 124 | begin |
| 125 | read_0 = insn[19:16]; /* Rn */ |
| 126 | read_1 = insn[3:0]; /* Rm */ |
| 127 | |
| 128 | op0_out = regs0; |
| 129 | op1_out = regs1; |
| 130 | end |
| 131 | `DECODE_ALU_BX: /* Branch and exchange */ |
| 132 | begin |
| 133 | read_0 = insn[3:0]; /* Rn */ |
| 134 | |
| 135 | op0_out = regs0; |
| 136 | end |
| 137 | `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */ |
| 138 | begin |
| 139 | read_0 = insn[19:16]; |
| 140 | read_1 = insn[3:0]; |
| 141 | read_2 = insn[15:12]; |
| 142 | |
| 143 | op0_out = regs0; |
| 144 | op1_out = regs1; |
| 145 | op2_out = regs2; |
| 146 | end |
| 147 | `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */ |
| 148 | begin |
| 149 | read_0 = insn[19:16]; |
| 150 | read_1 = insn[15:12]; |
| 151 | |
| 152 | op0_out = regs0; |
| 153 | op1_out = {24'b0, insn[11:8], insn[3:0]}; |
| 154 | op2_out = regs1; |
| 155 | end |
| 156 | `DECODE_ALU: /* ALU */ |
| 157 | begin |
| 158 | read_0 = insn[19:16]; /* Rn */ |
| 159 | read_1 = insn[3:0]; /* Rm */ |
| 160 | read_2 = insn[11:8]; /* Rs for shift */ |
| 161 | |
| 162 | op0_out = regs0; |
| 163 | if(insn[25]) begin /* the constant case */ |
| 164 | carry_out = incpsr[`CPSR_C]; |
| 165 | op1_out = rotate_res; |
| 166 | end else begin |
| 167 | carry_out = shift_cflag_out; |
| 168 | op1_out = shift_res; |
| 169 | end |
| 170 | end |
| 171 | `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */ |
| 172 | begin |
| 173 | /* eat shit */ |
| 174 | end |
| 175 | `DECODE_LDRSTR: /* Single data transfer */ |
| 176 | begin |
| 177 | read_0 = insn[19:16]; /* Rn */ |
| 178 | read_1 = insn[3:0]; /* Rm */ |
| 179 | read_2 = insn[15:12]; |
| 180 | |
| 181 | op0_out = regs0; |
| 182 | if(insn[25]) begin |
| 183 | op1_out = {20'b0, insn[11:0]}; |
| 184 | carry_out = incpsr[`CPSR_C]; |
| 185 | end else begin |
| 186 | op1_out = shift_res; |
| 187 | carry_out = shift_cflag_out; |
| 188 | end |
| 189 | op2_out = regs2; |
| 190 | end |
| 191 | `DECODE_LDMSTM: /* Block data transfer */ |
| 192 | begin |
| 193 | read_0 = insn[19:16]; |
| 194 | |
| 195 | op0_out = regs0; |
| 196 | op1_out = {16'b0, insn[15:0]}; |
| 197 | end |
| 198 | `DECODE_BRANCH: /* Branch */ |
| 199 | begin |
| 200 | op0_out = {{6{insn[23]}}, insn[23:0], 2'b0}; |
| 201 | end |
| 202 | `DECODE_LDCSTC: /* Coprocessor data transfer */ |
| 203 | begin |
| 204 | read_0 = insn[19:16]; |
| 205 | |
| 206 | op0_out = regs0; |
| 207 | op1_out = {24'b0, insn[7:0]}; |
| 208 | end |
| 209 | `DECODE_CDP: /* Coprocessor data op */ |
| 210 | begin |
| 211 | end |
| 212 | `DECODE_MRCMCR: /* Coprocessor register transfer */ |
| 213 | begin |
| 214 | read_0 = insn[15:12]; |
| 215 | |
| 216 | op0_out = regs0; |
| 217 | end |
| 218 | `DECODE_SWI: /* SWI */ |
| 219 | begin |
| 220 | end |
| 221 | default: |
| 222 | $display("Undecoded instruction"); |
| 223 | endcase |
| 224 | end |
| 225 | |
| 226 | |
| 227 | always @ (posedge clk) begin |
| 228 | op0 <= op0_out; /* Rn - always */ |
| 229 | op1 <= op1_out; /* 'operand 2' - Rm */ |
| 230 | op2 <= op2_out; /* thirdedge - Rs */ |
| 231 | carry <= carry_out; |
| 232 | outspsr <= inspsr; |
| 233 | end |
| 234 | |
| 235 | endmodule |
| 236 | |
| 237 | module IREALLYHATEARMSHIFT( |
| 238 | input [31:0] insn, |
| 239 | input [31:0] operand, |
| 240 | input [31:0] reg_amt, |
| 241 | input cflag_in, |
| 242 | output reg [31:0] res, |
| 243 | output reg cflag_out |
| 244 | ); |
| 245 | wire [5:0] shift_amt; |
| 246 | reg is_arith, is_rot; |
| 247 | wire rshift_cout; |
| 248 | wire [31:0] rshift_res; |
| 249 | |
| 250 | assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */ |
| 251 | : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */ |
| 252 | |
| 253 | SuckLessShifter barrel(.oper(operand), |
| 254 | .carryin(cflag_in), |
| 255 | .amt(shift_amt), |
| 256 | .is_arith(is_arith), |
| 257 | .is_rot(is_rot), |
| 258 | .res(rshift_res), |
| 259 | .carryout(rshift_cout)); |
| 260 | |
| 261 | always @(*) |
| 262 | case (insn[6:5]) |
| 263 | `SHIFT_LSL: begin |
| 264 | /* meaningless */ |
| 265 | is_rot = 1'b0; |
| 266 | is_arith = 1'b0; |
| 267 | end |
| 268 | `SHIFT_LSR: begin |
| 269 | is_rot = 1'b0; |
| 270 | is_arith = 1'b0; |
| 271 | end |
| 272 | `SHIFT_ASR: begin |
| 273 | is_rot = 1'b0; |
| 274 | is_arith = 1'b1; |
| 275 | end |
| 276 | `SHIFT_ROR: begin |
| 277 | is_rot = 1'b1; |
| 278 | is_arith = 1'b0; |
| 279 | end |
| 280 | endcase |
| 281 | |
| 282 | always @(*) |
| 283 | case (insn[6:5]) /* shift type */ |
| 284 | `SHIFT_LSL: |
| 285 | {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]}; |
| 286 | `SHIFT_LSR: begin |
| 287 | res = rshift_res; |
| 288 | cflag_out = rshift_cout; |
| 289 | end |
| 290 | `SHIFT_ASR: begin |
| 291 | res = rshift_res; |
| 292 | cflag_out = rshift_cout; |
| 293 | end |
| 294 | `SHIFT_ROR: begin |
| 295 | if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */ |
| 296 | res = {cflag_in, operand[31:1]}; |
| 297 | cflag_out = operand[0]; |
| 298 | end else begin |
| 299 | res = rshift_res; |
| 300 | cflag_out = rshift_cout; |
| 301 | end |
| 302 | end |
| 303 | endcase |
| 304 | endmodule |
| 305 | |
| 306 | module SuckLessShifter( |
| 307 | input [31:0] oper, |
| 308 | input carryin, |
| 309 | input [5:0] amt, |
| 310 | input is_arith, |
| 311 | input is_rot, |
| 312 | output wire [31:0] res, |
| 313 | output wire carryout |
| 314 | ); |
| 315 | |
| 316 | wire [32:0] stage1, stage2, stage3, stage4, stage5; |
| 317 | |
| 318 | wire pushbits = is_arith & oper[31]; |
| 319 | |
| 320 | /* do a barrel shift */ |
| 321 | assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin}; |
| 322 | assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1; |
| 323 | assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2; |
| 324 | assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3; |
| 325 | assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4; |
| 326 | assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5; |
| 327 | |
| 328 | endmodule |
| 329 | |
| 330 | module SuckLessRotator( |
| 331 | input [31:0] oper, |
| 332 | input [3:0] amt, |
| 333 | output wire [31:0] res |
| 334 | ); |
| 335 | |
| 336 | wire [31:0] stage1, stage2, stage3; |
| 337 | assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper; |
| 338 | assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1; |
| 339 | assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2; |
| 340 | assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3; |
| 341 | |
| 342 | endmodule |
| 343 | |