Fetch: Rewrite for the 317235784th time, this time based off a block diagram on paper...
[firearm.git] / Fetch.v
... / ...
CommitLineData
1module Fetch(
2 input clk,
3 input Nrst,
4
5 output wire [31:0] rd_addr,
6 output wire rd_req,
7 input rd_wait,
8 input [31:0] rd_data,
9
10 input stall,
11 input jmp,
12 input [31:0] jmppc,
13 output reg bubble = 1,
14 output reg [31:0] insn = 0,
15 output reg [31:0] pc = 32'hFFFFFFFC);
16
17 reg qjmp = 0; /* A jump has been queued up while we were waiting. */
18 reg [31:0] qjmppc;
19 always @(posedge clk or negedge Nrst)
20 if (!Nrst)
21 qjmp <= 0;
22 else if ((rd_wait || stall) && jmp)
23 {qjmp,qjmppc} <= {jmp, jmppc};
24 else if (!rd_wait && !stall && qjmp) /* It has already been intoed. */
25 {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
26
27 reg [31:0] reqpc;
28
29 /* Output latch logic */
30 assign rd_addr = reqpc;
31 assign rd_req = 1;
32 always @(posedge clk or negedge Nrst)
33 if (!Nrst) begin
34 bubble <= 1;
35 insn <= 0;
36 pc <= 32'h00000000;
37 end else if (!stall) begin
38 bubble <= (jmp || qjmp || rd_wait);
39 insn <= rd_data;
40 pc <= reqpc;
41 end
42
43 always @(posedge clk or negedge Nrst)
44 if (!Nrst)
45 reqpc <= 0;
46 else if (!stall && !rd_wait) begin
47 if (qjmp)
48 reqpc <= qjmppc;
49 else if (jmp)
50 reqpc <= jmppc;
51 else
52 reqpc <= reqpc + 4;
53 end
54endmodule
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