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1 | `include "ARM_Constants.v" | |
2 | ||
3 | `define SWP_READING 2'b01 | |
4 | `define SWP_WRITING 2'b10 | |
5 | ||
6 | `define LSRH_MEMIO 3'b001 | |
7 | `define LSRH_BASEWB 3'b010 | |
8 | `define LSRH_WBFLUSH 3'b100 | |
9 | ||
10 | `define LSR_MEMIO 4'b0001 | |
11 | `define LSR_STRB_WR 4'b0010 | |
12 | `define LSR_BASEWB 4'b0100 | |
13 | `define LSR_WBFLUSH 4'b1000 | |
14 | ||
15 | `define LSM_SETUP 4'b0001 | |
16 | `define LSM_MEMIO 4'b0010 | |
17 | `define LSM_BASEWB 4'b0100 | |
18 | `define LSM_WBFLUSH 4'b1000 | |
19 | ||
20 | ||
21 | module Memory( | |
22 | input clk, | |
23 | input Nrst, | |
24 | ||
25 | input flush, | |
26 | ||
27 | /* bus interface */ | |
28 | output reg [31:0] busaddr, | |
29 | output reg rd_req, | |
30 | output reg wr_req, | |
31 | input rw_wait, | |
32 | output reg [31:0] wr_data, | |
33 | input [31:0] rd_data, | |
34 | output reg [2:0] data_size, | |
35 | ||
36 | /* regfile interface */ | |
37 | output reg [3:0] st_read, | |
38 | input [31:0] st_data, | |
39 | ||
40 | /* Coprocessor interface */ | |
41 | output reg cp_req, | |
42 | input cp_ack, | |
43 | input cp_busy, | |
44 | output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */ | |
45 | input [31:0] cp_read, | |
46 | output reg [31:0] cp_write, | |
47 | ||
48 | /* stage inputs */ | |
49 | input inbubble, | |
50 | input [31:0] pc, | |
51 | input [31:0] insn, | |
52 | input [31:0] op0, | |
53 | input [31:0] op1, | |
54 | input [31:0] op2, | |
55 | input [31:0] spsr, | |
56 | input [31:0] cpsr, | |
57 | input cpsrup, | |
58 | input write_reg, | |
59 | input [3:0] write_num, | |
60 | input [31:0] write_data, | |
61 | ||
62 | /* outputs */ | |
63 | output reg outstall, | |
64 | output reg outbubble, | |
65 | output reg [31:0] outpc, | |
66 | output reg [31:0] outinsn, | |
67 | output reg out_write_reg = 1'b0, | |
68 | output reg [3:0] out_write_num = 4'bxxxx, | |
69 | output reg [31:0] out_write_data = 32'hxxxxxxxx, | |
70 | output reg [31:0] outspsr = 32'hxxxxxxxx, | |
71 | output reg [31:0] outcpsr = 32'hxxxxxxxx, | |
72 | output reg outcpsrup = 1'hx | |
73 | ); | |
74 | ||
75 | reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr; | |
76 | reg next_outcpsrup; | |
77 | reg [31:0] prevaddr; | |
78 | reg [3:0] next_regsel, cur_reg, prev_reg; | |
79 | reg next_writeback; | |
80 | ||
81 | reg next_outbubble; | |
82 | reg next_write_reg; | |
83 | reg [3:0] next_write_num; | |
84 | reg [31:0] next_write_data; | |
85 | ||
86 | reg [3:0] lsr_state = 4'b0001, next_lsr_state; | |
87 | reg [31:0] align_s1, align_s2, align_rddata; | |
88 | ||
89 | reg [2:0] lsrh_state = 3'b001, next_lsrh_state; | |
90 | reg [31:0] lsrh_rddata; | |
91 | reg [15:0] lsrh_rddata_s1; | |
92 | reg [7:0] lsrh_rddata_s2; | |
93 | ||
94 | reg [15:0] regs, next_regs; | |
95 | reg [3:0] lsm_state = 4'b0001, next_lsm_state; | |
96 | reg [5:0] offset, prev_offset, offset_sel; | |
97 | ||
98 | reg [31:0] swp_oldval, next_swp_oldval; | |
99 | reg [1:0] swp_state = 2'b01, next_swp_state; | |
100 | ||
101 | reg do_rd_data_latch; | |
102 | reg [31:0] rd_data_latch = 32'hxxxxxxxx; | |
103 | ||
104 | always @(posedge clk) | |
105 | begin | |
106 | outpc <= pc; | |
107 | outinsn <= insn; | |
108 | outbubble <= next_outbubble; | |
109 | out_write_reg <= next_write_reg; | |
110 | out_write_num <= next_write_num; | |
111 | out_write_data <= next_write_data; | |
112 | regs <= next_regs; | |
113 | prev_reg <= cur_reg; | |
114 | if (!rw_wait) | |
115 | prev_offset <= offset; | |
116 | prev_raddr <= raddr; | |
117 | outcpsr <= next_outcpsr; | |
118 | outspsr <= spsr; | |
119 | outcpsrup <= next_outcpsrup; | |
120 | swp_state <= next_swp_state; | |
121 | lsm_state <= next_lsm_state; | |
122 | lsr_state <= next_lsr_state; | |
123 | lsrh_state <= next_lsrh_state; | |
124 | if (do_rd_data_latch) | |
125 | rd_data_latch <= rd_data; | |
126 | prevaddr <= addr; | |
127 | end | |
128 | ||
129 | reg delayedflush = 0; | |
130 | always @(posedge clk) | |
131 | if (flush && outstall /* halp! I can't do it now, maybe later? */) | |
132 | delayedflush <= 1; | |
133 | else if (!outstall /* anything has been handled this time around */) | |
134 | delayedflush <= 0; | |
135 | ||
136 | /* Drive the state machines and stall. */ | |
137 | always @(*) | |
138 | begin | |
139 | outstall = 1'b0; | |
140 | next_lsm_state = lsm_state; | |
141 | next_lsr_state = lsr_state; | |
142 | next_lsrh_state = lsrh_state; | |
143 | next_swp_state = swp_state; | |
144 | casez(insn) | |
145 | `DECODE_ALU_SWP: if(!inbubble) begin | |
146 | case(swp_state) | |
147 | `SWP_READING: begin | |
148 | outstall = 1'b1; | |
149 | if (!rw_wait) | |
150 | next_swp_state = `SWP_WRITING; | |
151 | $display("SWP: read stage"); | |
152 | end | |
153 | `SWP_WRITING: begin | |
154 | outstall = rw_wait; | |
155 | if(!rw_wait) | |
156 | next_swp_state = `SWP_READING; | |
157 | $display("SWP: write stage"); | |
158 | end | |
159 | default: begin | |
160 | outstall = 1'bx; | |
161 | next_swp_state = 2'bxx; | |
162 | end | |
163 | endcase | |
164 | end | |
165 | `DECODE_ALU_MULT: begin end | |
166 | `DECODE_ALU_HDATA_REG, | |
167 | `DECODE_ALU_HDATA_IMM: if(!inbubble) begin | |
168 | case(lsrh_state) | |
169 | `LSRH_MEMIO: begin | |
170 | outstall = rw_wait; | |
171 | if(insn[21] | !insn[24]) begin | |
172 | outstall = 1'b1; | |
173 | if(!rw_wait) | |
174 | next_lsrh_state = `LSRH_BASEWB; | |
175 | end | |
176 | ||
177 | if (flush) /* special case! */ begin | |
178 | outstall = 1'b0; | |
179 | next_lsrh_state = `LSRH_MEMIO; | |
180 | end | |
181 | ||
182 | $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req); | |
183 | end | |
184 | `LSRH_BASEWB: begin | |
185 | outstall = 1'b1; | |
186 | next_lsrh_state = `LSRH_WBFLUSH; | |
187 | end | |
188 | `LSRH_WBFLUSH: begin | |
189 | outstall = 1'b0; | |
190 | next_lsrh_state = `LSRH_MEMIO; | |
191 | end | |
192 | default: begin | |
193 | outstall = 1'bx; | |
194 | next_lsrh_state = 3'bxxx; | |
195 | end | |
196 | endcase | |
197 | end | |
198 | `DECODE_LDRSTR_UNDEFINED: begin end | |
199 | `DECODE_LDRSTR: if(!inbubble) begin | |
200 | outstall = rw_wait; | |
201 | case(lsr_state) | |
202 | `LSR_MEMIO: begin | |
203 | outstall = rw_wait; | |
204 | next_lsr_state = `LSR_MEMIO; | |
205 | if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */ | |
206 | outstall = 1'b1; | |
207 | if (!rw_wait) | |
208 | next_lsr_state = `LSR_STRB_WR; | |
209 | end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */ | |
210 | outstall = 1'b1; | |
211 | if (!rw_wait) | |
212 | next_lsr_state = `LSR_BASEWB; | |
213 | end | |
214 | ||
215 | if (flush) begin | |
216 | outstall = 1'b0; | |
217 | next_lsr_state = `LSR_MEMIO; | |
218 | end | |
219 | $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait); | |
220 | end | |
221 | `LSR_STRB_WR: begin | |
222 | outstall = 1; | |
223 | if(insn[21] /* W */ | !insn[24] /* P */) begin | |
224 | if(!rw_wait) | |
225 | next_lsr_state = `LSR_BASEWB; | |
226 | end else if (!rw_wait) | |
227 | next_lsr_state = `LSR_WBFLUSH; | |
228 | $display("LDRSTR: Handling STRB"); | |
229 | end | |
230 | `LSR_BASEWB: begin | |
231 | outstall = 1; | |
232 | next_lsr_state = `LSR_WBFLUSH; | |
233 | end | |
234 | `LSR_WBFLUSH: begin | |
235 | outstall = 0; | |
236 | next_lsr_state = `LSR_MEMIO; | |
237 | end | |
238 | default: begin | |
239 | outstall = 1'bx; | |
240 | next_lsr_state = 4'bxxxx; | |
241 | end | |
242 | endcase | |
243 | $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall); | |
244 | end | |
245 | `DECODE_LDMSTM: if(!inbubble) begin | |
246 | outstall = rw_wait; | |
247 | case(lsm_state) | |
248 | `LSM_SETUP: begin | |
249 | outstall = 1'b1; | |
250 | next_lsm_state = `LSM_MEMIO; | |
251 | if (flush) begin | |
252 | outstall = 1'b0; | |
253 | next_lsm_state = `LSM_SETUP; | |
254 | end | |
255 | $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]); | |
256 | end | |
257 | `LSM_MEMIO: begin | |
258 | outstall = 1'b1; | |
259 | if(next_regs == 16'b0) begin | |
260 | next_lsm_state = `LSM_BASEWB; | |
261 | end | |
262 | ||
263 | $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr); | |
264 | end | |
265 | `LSM_BASEWB: begin | |
266 | outstall = 1; | |
267 | next_lsm_state = `LSM_WBFLUSH; | |
268 | $display("LDMSTM: Stage 3: Writing back"); | |
269 | end | |
270 | `LSM_WBFLUSH: begin | |
271 | outstall = 0; | |
272 | next_lsm_state = `LSM_SETUP; | |
273 | end | |
274 | default: begin | |
275 | outstall = 1'bx; | |
276 | next_lsm_state = 4'bxxxx; | |
277 | end | |
278 | endcase | |
279 | $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall); | |
280 | end | |
281 | `DECODE_LDCSTC: if(!inbubble) begin | |
282 | $display("WARNING: Unimplemented LDCSTC"); | |
283 | end | |
284 | `DECODE_CDP: if (!inbubble) begin | |
285 | if (cp_busy) begin | |
286 | outstall = 1; | |
287 | end | |
288 | if (!cp_ack) begin | |
289 | /* XXX undefined instruction trap */ | |
290 | $display("WARNING: Possible CDP undefined instruction"); | |
291 | end | |
292 | end | |
293 | `DECODE_MRCMCR: if (!inbubble) begin | |
294 | if (cp_busy) begin | |
295 | outstall = 1; | |
296 | end | |
297 | if (!cp_ack) begin | |
298 | $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy); | |
299 | end | |
300 | $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy); | |
301 | end | |
302 | default: begin end | |
303 | endcase | |
304 | end | |
305 | ||
306 | /* Coprocessor input. */ | |
307 | always @(*) | |
308 | begin | |
309 | cp_req = 0; | |
310 | cp_rnw = 1'bx; | |
311 | cp_write = 32'hxxxxxxxx; | |
312 | casez (insn) | |
313 | `DECODE_CDP: if(!inbubble) begin | |
314 | cp_req = 1; | |
315 | end | |
316 | `DECODE_MRCMCR: if(!inbubble) begin | |
317 | cp_req = 1; | |
318 | cp_rnw = insn[20] /* L */; | |
319 | if (insn[20] == 0 /* store to coprocessor */) | |
320 | cp_write = op0; | |
321 | end | |
322 | endcase | |
323 | end | |
324 | ||
325 | /* Register output logic. */ | |
326 | always @(*) | |
327 | begin | |
328 | next_write_reg = write_reg; | |
329 | next_write_num = write_num; | |
330 | next_write_data = write_data; | |
331 | next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr; | |
332 | next_outcpsrup = cpsrup; | |
333 | ||
334 | casez(insn) | |
335 | `DECODE_ALU_SWP: if (!inbubble) begin | |
336 | next_write_reg = 1'bx; | |
337 | next_write_num = 4'bxxxx; | |
338 | next_write_data = 32'hxxxxxxxx; | |
339 | case(swp_state) | |
340 | `SWP_READING: | |
341 | next_write_reg = 1'b0; | |
342 | `SWP_WRITING: begin | |
343 | next_write_reg = 1'b1; | |
344 | next_write_num = insn[15:12]; | |
345 | next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval; | |
346 | end | |
347 | default: begin end | |
348 | endcase | |
349 | end | |
350 | `DECODE_ALU_MULT: begin end | |
351 | `DECODE_ALU_HDATA_REG, | |
352 | `DECODE_ALU_HDATA_IMM: if(!inbubble) begin | |
353 | next_write_reg = 1'bx; | |
354 | next_write_num = 4'bxxxx; | |
355 | next_write_data = 32'hxxxxxxxx; | |
356 | case(lsrh_state) | |
357 | `LSRH_MEMIO: begin | |
358 | next_write_num = insn[15:12]; | |
359 | next_write_data = lsrh_rddata; | |
360 | if(insn[20]) begin | |
361 | next_write_reg = 1'b1; | |
362 | end | |
363 | end | |
364 | `LSRH_BASEWB: begin | |
365 | next_write_reg = 1'b1; | |
366 | next_write_num = insn[19:16]; | |
367 | next_write_data = addr; | |
368 | end | |
369 | `LSRH_WBFLUSH: | |
370 | next_write_reg = 1'b0; | |
371 | default: begin end | |
372 | endcase | |
373 | end | |
374 | `DECODE_LDRSTR_UNDEFINED: begin end | |
375 | `DECODE_LDRSTR: if(!inbubble) begin | |
376 | next_write_reg = 1'bx; | |
377 | next_write_num = 4'bxxxx; | |
378 | next_write_data = 32'hxxxxxxxx; | |
379 | case(lsr_state) | |
380 | `LSR_MEMIO: begin | |
381 | next_write_reg = insn[20] /* L */; | |
382 | next_write_num = insn[15:12]; | |
383 | if(insn[20] /* L */) begin | |
384 | next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata; | |
385 | end | |
386 | end | |
387 | `LSR_STRB_WR: | |
388 | next_write_reg = 1'b0; | |
389 | `LSR_BASEWB: begin | |
390 | next_write_reg = 1'b1; | |
391 | next_write_num = insn[19:16]; | |
392 | next_write_data = addr; | |
393 | end | |
394 | `LSR_WBFLUSH: | |
395 | next_write_reg = 1'b0; | |
396 | default: begin end | |
397 | endcase | |
398 | end | |
399 | `DECODE_LDMSTM: if(!inbubble) begin | |
400 | next_write_reg = 1'bx; | |
401 | next_write_num = 4'bxxxx; | |
402 | next_write_data = 32'hxxxxxxxx; | |
403 | case(lsm_state) | |
404 | `LSM_SETUP: | |
405 | next_write_reg = 1'b0; | |
406 | `LSM_MEMIO: begin | |
407 | if(insn[20]) begin | |
408 | next_write_reg = !rw_wait; | |
409 | next_write_num = cur_reg; | |
410 | next_write_data = rd_data; | |
411 | end else | |
412 | next_write_reg = 1'b0; | |
413 | end | |
414 | `LSM_BASEWB: begin | |
415 | next_write_reg = insn[21] /* writeback */; | |
416 | next_write_num = insn[19:16]; | |
417 | next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset}; | |
418 | if(cur_reg == 4'hF && insn[22]) begin | |
419 | next_outcpsr = spsr; | |
420 | next_outcpsrup = 1; | |
421 | end | |
422 | end | |
423 | `LSM_WBFLUSH: | |
424 | next_write_reg = 1'b0; | |
425 | default: begin end | |
426 | endcase | |
427 | end | |
428 | `DECODE_MRCMCR: if(!inbubble) begin | |
429 | next_write_reg = 1'bx; | |
430 | next_write_num = 4'bxxxx; | |
431 | next_write_data = 32'hxxxxxxxx; | |
432 | next_outcpsr = 32'hxxxxxxxx; | |
433 | next_outcpsrup = 1'bx; | |
434 | if (insn[20] == 1 /* load from coprocessor */) | |
435 | if (insn[15:12] != 4'hF /* Fuck you ARM */) begin | |
436 | next_write_reg = 1'b1; | |
437 | next_write_num = insn[15:12]; | |
438 | next_write_data = cp_read; | |
439 | end else begin | |
440 | next_outcpsr = {cp_read[31:28], cpsr[27:0]}; | |
441 | next_outcpsrup = 1; | |
442 | end | |
443 | end | |
444 | endcase | |
445 | end | |
446 | ||
447 | /* Bus control logic. */ | |
448 | always @(*) | |
449 | begin | |
450 | rd_req = 1'b0; | |
451 | wr_req = 1'b0; | |
452 | wr_data = 32'hxxxxxxxx; | |
453 | offset = prev_offset; | |
454 | addr = prevaddr; | |
455 | raddr = 32'hxxxxxxxx; | |
456 | busaddr = 32'hxxxxxxxx; | |
457 | data_size = 3'bxxx; | |
458 | ||
459 | casez(insn) | |
460 | `DECODE_ALU_SWP: if(!inbubble) begin | |
461 | busaddr = {op0[31:2], 2'b0}; | |
462 | data_size = insn[22] ? 3'b001 : 3'b100; | |
463 | case(swp_state) | |
464 | `SWP_READING: | |
465 | rd_req = 1'b1; | |
466 | `SWP_WRITING: begin | |
467 | wr_req = 1'b1; | |
468 | wr_data = insn[22] ? {4{op1[7:0]}} : op1; | |
469 | end | |
470 | default: begin end | |
471 | endcase | |
472 | end | |
473 | `DECODE_ALU_MULT: begin end | |
474 | `DECODE_ALU_HDATA_REG, | |
475 | `DECODE_ALU_HDATA_IMM: if(!inbubble) begin | |
476 | addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ | |
477 | raddr = insn[24] ? op0 : addr; /* pre/post increment */ | |
478 | busaddr = raddr; | |
479 | /* rotate to correct position */ | |
480 | case(insn[6:5]) | |
481 | 2'b01: begin /* unsigned half */ | |
482 | wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */ | |
483 | data_size = 3'b010; | |
484 | end | |
485 | 2'b10: begin /* signed byte */ | |
486 | wr_data = {4{op2[7:0]}}; | |
487 | data_size = 3'b001; | |
488 | end | |
489 | 2'b11: begin /* signed half */ | |
490 | wr_data = {2{op2[15:0]}}; | |
491 | data_size = 3'b010; | |
492 | end | |
493 | default: begin | |
494 | wr_data = 32'hxxxxxxxx; | |
495 | data_size = 3'bxxx; | |
496 | end | |
497 | endcase | |
498 | ||
499 | case(lsrh_state) | |
500 | `LSRH_MEMIO: begin | |
501 | rd_req = insn[20]; | |
502 | wr_req = ~insn[20]; | |
503 | end | |
504 | `LSRH_BASEWB: begin end | |
505 | `LSRH_WBFLUSH: begin end | |
506 | default: begin end | |
507 | endcase | |
508 | end | |
509 | `DECODE_LDRSTR_UNDEFINED: begin end | |
510 | `DECODE_LDRSTR: if(!inbubble) begin | |
511 | addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ | |
512 | raddr = insn[24] ? addr : op0; /* pre/post increment */ | |
513 | busaddr = raddr; | |
514 | wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2; | |
515 | data_size = insn[22] ? 3'b001 : 3'b100; | |
516 | case (lsr_state) | |
517 | `LSR_MEMIO: begin | |
518 | rd_req = insn[20] /* L */ || insn[22] /* B */; | |
519 | wr_req = !insn[20] /* L */ && !insn[22]/* B */; | |
520 | end | |
521 | `LSR_STRB_WR: begin | |
522 | wr_req = 1; | |
523 | case (busaddr[1:0]) | |
524 | 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]}; | |
525 | 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]}; | |
526 | 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]}; | |
527 | 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]}; | |
528 | endcase | |
529 | end | |
530 | `LSR_BASEWB: begin end | |
531 | `LSR_WBFLUSH: begin end | |
532 | default: begin end | |
533 | endcase | |
534 | end | |
535 | `DECODE_LDMSTM: if (!inbubble) begin | |
536 | data_size = 3'b100; | |
537 | case (lsm_state) | |
538 | `LSM_SETUP: | |
539 | offset = 6'b0; | |
540 | `LSM_MEMIO: begin | |
541 | rd_req = insn[20]; | |
542 | wr_req = ~insn[20]; | |
543 | wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data; | |
544 | offset = prev_offset + 6'h4; | |
545 | offset_sel = insn[24] ? offset : prev_offset; | |
546 | raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel}; | |
547 | busaddr = raddr; | |
548 | end | |
549 | `LSM_BASEWB: begin end | |
550 | `LSM_WBFLUSH: begin end | |
551 | default: begin end | |
552 | endcase | |
553 | end | |
554 | `DECODE_LDCSTC: begin end | |
555 | `DECODE_CDP: begin end | |
556 | `DECODE_MRCMCR: begin end | |
557 | default: begin end | |
558 | endcase | |
559 | end | |
560 | ||
561 | always @(*) | |
562 | begin | |
563 | st_read = 4'hx; | |
564 | do_rd_data_latch = 0; | |
565 | ||
566 | next_outbubble = inbubble; | |
567 | next_regs = regs; | |
568 | ||
569 | offset = prev_offset; | |
570 | lsrh_rddata = 32'hxxxxxxxx; | |
571 | lsrh_rddata_s1 = 16'hxxxx; | |
572 | lsrh_rddata_s2 = 8'hxx; | |
573 | next_swp_oldval = swp_oldval; | |
574 | cur_reg = prev_reg; | |
575 | ||
576 | /* XXX shit not given about endianness */ | |
577 | casez(insn) | |
578 | `DECODE_ALU_SWP: if(!inbubble) begin | |
579 | next_outbubble = rw_wait; | |
580 | case(swp_state) | |
581 | `SWP_READING: | |
582 | if(!rw_wait) | |
583 | next_swp_oldval = rd_data; | |
584 | `SWP_WRITING: begin end | |
585 | default: begin end | |
586 | endcase | |
587 | end | |
588 | `DECODE_ALU_MULT: begin end | |
589 | `DECODE_ALU_HDATA_REG, | |
590 | `DECODE_ALU_HDATA_IMM: if(!inbubble) begin | |
591 | next_outbubble = rw_wait; | |
592 | ||
593 | /* rotate to correct position */ | |
594 | case(insn[6:5]) | |
595 | 2'b01: begin /* unsigned half */ | |
596 | lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]}; | |
597 | end | |
598 | 2'b10: begin /* signed byte */ | |
599 | lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0]; | |
600 | lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0]; | |
601 | lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2}; | |
602 | end | |
603 | 2'b11: begin /* signed half */ | |
604 | lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]}; | |
605 | end | |
606 | default: begin | |
607 | lsrh_rddata = 32'hxxxxxxxx; | |
608 | end | |
609 | endcase | |
610 | ||
611 | case(lsrh_state) | |
612 | `LSRH_MEMIO: begin end | |
613 | `LSRH_BASEWB: | |
614 | next_outbubble = 1'b0; | |
615 | `LSRH_WBFLUSH: begin end | |
616 | default: begin end | |
617 | endcase | |
618 | end | |
619 | `DECODE_LDRSTR_UNDEFINED: begin end | |
620 | `DECODE_LDRSTR: if(!inbubble) begin | |
621 | next_outbubble = rw_wait; | |
622 | /* rotate to correct position */ | |
623 | align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data; | |
624 | align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1; | |
625 | /* select byte or word */ | |
626 | align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2; | |
627 | case(lsr_state) | |
628 | `LSR_MEMIO: | |
629 | if (insn[22] /* B */ && !insn[20] /* L */) | |
630 | do_rd_data_latch = 1; | |
631 | `LSR_STRB_WR: begin end | |
632 | `LSR_BASEWB: | |
633 | next_outbubble = 0; | |
634 | `LSR_WBFLUSH: begin end | |
635 | default: begin end | |
636 | endcase | |
637 | end | |
638 | /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */ | |
639 | `DECODE_LDMSTM: if(!inbubble) begin | |
640 | next_outbubble = rw_wait; | |
641 | case(lsm_state) | |
642 | `LSM_SETUP: begin | |
643 | // next_regs = insn[23] ? op1[15:0] : op1[0:15]; | |
644 | /** verilator can suck my dick */ | |
645 | next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7], | |
646 | op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]}; | |
647 | end | |
648 | `LSM_MEMIO: begin | |
649 | casez(regs) | |
650 | 16'b???????????????1: begin | |
651 | cur_reg = 4'h0; | |
652 | next_regs = {regs[15:1], 1'b0}; | |
653 | end | |
654 | 16'b??????????????10: begin | |
655 | cur_reg = 4'h1; | |
656 | next_regs = {regs[15:2], 2'b0}; | |
657 | end | |
658 | 16'b?????????????100: begin | |
659 | cur_reg = 4'h2; | |
660 | next_regs = {regs[15:3], 3'b0}; | |
661 | end | |
662 | 16'b????????????1000: begin | |
663 | cur_reg = 4'h3; | |
664 | next_regs = {regs[15:4], 4'b0}; | |
665 | end | |
666 | 16'b???????????10000: begin | |
667 | cur_reg = 4'h4; | |
668 | next_regs = {regs[15:5], 5'b0}; | |
669 | end | |
670 | 16'b??????????100000: begin | |
671 | cur_reg = 4'h5; | |
672 | next_regs = {regs[15:6], 6'b0}; | |
673 | end | |
674 | 16'b?????????1000000: begin | |
675 | cur_reg = 4'h6; | |
676 | next_regs = {regs[15:7], 7'b0}; | |
677 | end | |
678 | 16'b????????10000000: begin | |
679 | cur_reg = 4'h7; | |
680 | next_regs = {regs[15:8], 8'b0}; | |
681 | end | |
682 | 16'b???????100000000: begin | |
683 | cur_reg = 4'h8; | |
684 | next_regs = {regs[15:9], 9'b0}; | |
685 | end | |
686 | 16'b??????1000000000: begin | |
687 | cur_reg = 4'h9; | |
688 | next_regs = {regs[15:10], 10'b0}; | |
689 | end | |
690 | 16'b?????10000000000: begin | |
691 | cur_reg = 4'hA; | |
692 | next_regs = {regs[15:11], 11'b0}; | |
693 | end | |
694 | 16'b????100000000000: begin | |
695 | cur_reg = 4'hB; | |
696 | next_regs = {regs[15:12], 12'b0}; | |
697 | end | |
698 | 16'b???1000000000000: begin | |
699 | cur_reg = 4'hC; | |
700 | next_regs = {regs[15:13], 13'b0}; | |
701 | end | |
702 | 16'b??10000000000000: begin | |
703 | cur_reg = 4'hD; | |
704 | next_regs = {regs[15:14], 14'b0}; | |
705 | end | |
706 | 16'b?100000000000000: begin | |
707 | cur_reg = 4'hE; | |
708 | next_regs = {regs[15], 15'b0}; | |
709 | end | |
710 | 16'b1000000000000000: begin | |
711 | cur_reg = 4'hF; | |
712 | next_regs = 16'b0; | |
713 | end | |
714 | default: begin | |
715 | cur_reg = 4'hx; | |
716 | next_regs = 16'b0; | |
717 | end | |
718 | endcase | |
719 | cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg; | |
720 | ||
721 | if (rw_wait) begin | |
722 | next_regs = regs; | |
723 | cur_reg = prev_reg; /* whoops, do this one again */ | |
724 | end | |
725 | ||
726 | st_read = cur_reg; | |
727 | end | |
728 | `LSM_BASEWB: | |
729 | next_outbubble = 0; | |
730 | `LSM_WBFLUSH: begin end | |
731 | default: $stop; | |
732 | endcase | |
733 | end | |
734 | `DECODE_LDCSTC: begin end | |
735 | `DECODE_CDP: if(!inbubble) begin | |
736 | if (cp_busy) begin | |
737 | next_outbubble = 1; | |
738 | end | |
739 | end | |
740 | `DECODE_MRCMCR: if(!inbubble) begin | |
741 | if (cp_busy) begin | |
742 | next_outbubble = 1; | |
743 | end | |
744 | end | |
745 | default: begin end | |
746 | endcase | |
747 | ||
748 | if ((flush || delayedflush) && !outstall) | |
749 | next_outbubble = 1'b1; | |
750 | end | |
751 | endmodule |