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tests: Add the new testbench.
[firearm.git] / tests / anulib.S
... / ...
CommitLineData
1 .text
2 .globl _start
3_start:
4 ldr sp, =0x3FFC
5 bl main
61: b 1b
7
8 .globl putc
9putc:
10 mcr 5, 0, r0, c0, c0
11 mov pc, lr
FireARM pipelined ARM-like CPU implementation in Verilog
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