Console: Put the core in its own clock domain.
[firearm.git] / system.v
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1`define BUS_ICACHE 1
2`define BUS_DCACHE 0
3
4module System(input clk, input rst
5`ifdef verilator
6`else
7 , output wire [8:0] sys_odata,
8 input [8:0] sys_idata,
9 output wire sys_tookdata
10`endif
11 );
12
13 wire [7:0] bus_req;
14 wire [7:0] bus_ack;
15 wire [31:0] bus_addr;
16 wire [31:0] bus_rdata;
17 wire [31:0] bus_wdata;
18 wire bus_rd, bus_wr;
19 wire bus_ready;
20
21 wire bus_req_icache;
22 wire bus_req_dcache;
23 assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
24 wire bus_ack_icache = bus_ack[`BUS_ICACHE];
25 wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
26
27 wire [31:0] bus_addr_icache;
28 wire [31:0] bus_wdata_icache;
29 wire bus_rd_icache;
30 wire bus_wr_icache;
31
32 wire [31:0] bus_addr_dcache;
33 wire [31:0] bus_wdata_dcache;
34 wire bus_rd_dcache;
35 wire bus_wr_dcache;
36
37 wire [31:0] bus_rdata_blockram;
38 wire bus_ready_blockram;
39
40 assign bus_addr = bus_addr_icache | bus_addr_dcache;
41 assign bus_rdata = bus_rdata_blockram;
42 assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
43 assign bus_rd = bus_rd_icache | bus_rd_dcache;
44 assign bus_wr = bus_wr_icache | bus_wr_dcache;
45 assign bus_ready = bus_ready_blockram;
46
47 wire [31:0] icache_rd_addr;
48 wire icache_rd_req;
49 wire icache_rd_wait;
50 wire [31:0] icache_rd_data;
51
52 wire [31:0] dcache_addr;
53 wire dcache_rd_req, dcache_wr_req;
54 wire dcache_rw_wait;
55 wire [31:0] dcache_wr_data, dcache_rd_data;
56
57 wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
58 wire decode_out_carry;
59
60 wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
61 wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
62 wire regfile_write;
63 wire [3:0] regfile_write_reg;
64 wire [31:0] regfile_write_data;
65
66 wire execute_out_write_reg;
67 wire [3:0] execute_out_write_num;
68 wire [31:0] execute_out_write_data;
69 wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
70 wire [31:0] execute_out_cpsr, execute_out_spsr;
71 wire execute_out_cpsrup;
72
73 wire jmp_out_execute, jmp_out_writeback;
74 wire [31:0] jmppc_out_execute, jmppc_out_writeback;
75 wire jmp = jmp_out_execute | jmp_out_writeback;
76 wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
77
78 wire memory_out_write_reg;
79 wire [3:0] memory_out_write_num;
80 wire [31:0] memory_out_write_data;
81 wire [31:0] memory_out_cpsr, memory_out_spsr;
82 wire memory_out_cpsrup;
83
84 wire [31:0] writeback_out_cpsr, writeback_out_spsr;
85
86 wire cp_ack_terminal;
87 wire cp_busy_terminal;
88 wire [31:0] cp_read_terminal;
89
90 wire cp_req;
91 wire [31:0] cp_insn;
92 wire cp_ack = cp_ack_terminal;
93 wire cp_busy = cp_busy_terminal;
94 wire cp_rnw;
95 wire [31:0] cp_read = cp_read_terminal;
96 wire [31:0] cp_write;
97
98 wire stall_cause_issue;
99 wire stall_cause_execute;
100 wire stall_cause_memory;
101 wire bubble_out_fetch;
102 wire bubble_out_issue;
103 wire bubble_out_execute;
104 wire bubble_out_memory;
105 wire [31:0] insn_out_fetch;
106 wire [31:0] insn_out_issue;
107 wire [31:0] insn_out_execute;
108 wire [31:0] insn_out_memory;
109 wire [31:0] pc_out_fetch;
110 wire [31:0] pc_out_issue;
111 wire [31:0] pc_out_execute;
112 wire [31:0] pc_out_memory;
113
114 wire execute_out_backflush;
115 wire writeback_out_backflush;
116
117 BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
118
119 ICache icache(
120 .clk(clk),
121 /* XXX reset? */
122 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
123 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
124 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
125 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
126 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
127 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
128
129 DCache dcache(
130 .clk(clk),
131 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
132 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
133 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
134 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
135 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
136 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
137
138`ifdef verilator
139 BigBlockRAM
140`else
141 BlockRAM
142`endif
143 blockram(
144 .clk(clk),
145 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
146 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
147 .bus_ready(bus_ready_blockram));
148
149 Fetch fetch(
150 .clk(clk),
151 .Nrst(~rst),
152 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
153 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
154 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
155 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
156 .pc(pc_out_fetch));
157
158 Issue issue(
159 .clk(clk),
160 .Nrst(~rst),
161 .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
162 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
163 .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
164 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
165 .outpc(pc_out_issue), .outinsn(insn_out_issue));
166
167 RegFile regfile(
168 .clk(clk), .Nrst(~rst),
169 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
170 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
171 .spsr(regfile_spsr),
172 .write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
173
174 Decode decode(
175 .clk(clk),
176 .stall(stall_cause_execute),
177 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
178 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
179 .carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
180 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
181 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
182
183 Execute execute(
184 .clk(clk), .Nrst(~rst),
185 .stall(stall_cause_memory), .flush(writeback_out_backflush),
186 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
187 .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
188 .op2(decode_out_op2), .carry(decode_out_carry),
189 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
190 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
191 .write_data(execute_out_write_data),
192 .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
193 .outpc(pc_out_execute), .outinsn(insn_out_execute),
194 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
195 .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
196 assign execute_out_backflush = jmp;
197
198 assign cp_insn = insn_out_execute;
199 Memory memory(
200 .clk(clk), .Nrst(~rst),
201 /* stall? */ .flush(writeback_out_backflush),
202 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
203 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
204 .st_read(regfile_read_3), .st_data(regfile_rdata_3),
205 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
206 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
207 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
208 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
209 .outstall(stall_cause_memory), .outbubble(bubble_out_memory),
210 .outpc(pc_out_memory), .outinsn(insn_out_memory),
211 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
212 .out_write_data(memory_out_write_data),
213 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
214 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
215
216 Terminal terminal(
217 .clk(clk),
218 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
219 .cp_read(cp_read_terminal), .cp_write(cp_write)
220`ifdef verilator
221`else
222 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
223`endif
224 );
225
226 Writeback writeback(
227 .clk(clk),
228 .inbubble(bubble_out_memory),
229 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
230 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
231 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
232 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
233 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
234 assign writeback_out_backflush = jmp_out_writeback;
235
236 reg [31:0] clockno = 0;
237 always @(posedge clk)
238 begin
239 clockno <= clockno + 1;
240 $display("------------------------------------------------------------------------------");
241 $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
242 $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
243 $display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
244 $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
245 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
246 $display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
247 end
248endmodule
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