]>
Commit | Line | Data |
---|---|---|
1 | module Fetch( | |
2 | input clk, | |
3 | input Nrst, | |
4 | ||
5 | output wire [31:0] ic__rd_addr_0a, | |
6 | output wire ic__rd_req_0a, | |
7 | input ic__rd_wait_0a, | |
8 | input [31:0] ic__rd_data_0a, | |
9 | ||
10 | input stall_0a, | |
11 | input jmp_0a, | |
12 | input [31:0] jmppc_0a, | |
13 | output reg bubble_1a = 1, | |
14 | output reg [31:0] insn_1a = 0, | |
15 | output reg [31:0] pc_1a = 32'hFFFFFFFC); | |
16 | ||
17 | reg qjmp = 0; /* A jump has been queued up while we were waiting. */ | |
18 | reg [31:0] qjmppc; | |
19 | always @(posedge clk or negedge Nrst) | |
20 | if (!Nrst) | |
21 | qjmp <= 0; | |
22 | else if ((ic__rd_wait_0a || stall_0a) && jmp_0a) | |
23 | {qjmp,qjmppc} <= {jmp_0a, jmppc_0a}; | |
24 | else if (!ic__rd_wait_0a && !stall_0a && qjmp) /* It has already been intoed. */ | |
25 | {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx}; | |
26 | ||
27 | reg [31:0] reqpc_0a; | |
28 | ||
29 | /* Output latch logic */ | |
30 | assign ic__rd_addr_0a = reqpc_0a; | |
31 | assign ic__rd_req_0a = 1; | |
32 | always @(posedge clk or negedge Nrst) | |
33 | if (!Nrst) begin | |
34 | bubble_1a <= 1; | |
35 | insn_1a <= 32'h00000000; | |
36 | pc_1a <= 32'h00000000; | |
37 | end else if (!stall_0a) begin | |
38 | bubble_1a <= (jmp_0a || qjmp || ic__rd_wait_0a); | |
39 | insn_1a <= ic__rd_data_0a; | |
40 | pc_1a <= reqpc_0a; | |
41 | end | |
42 | ||
43 | always @(posedge clk or negedge Nrst) | |
44 | if (!Nrst) | |
45 | reqpc_0a <= 0; | |
46 | else if (!stall_0a && !ic__rd_wait_0a) begin | |
47 | if (qjmp) | |
48 | reqpc_0a <= qjmppc; | |
49 | else if (jmp_0a) | |
50 | reqpc_0a <= jmppc_0a; | |
51 | else | |
52 | reqpc_0a <= reqpc_0a + 4; | |
53 | end | |
54 | endmodule |