| 1 | module Terminal( |
| 2 | input clk, |
| 3 | |
| 4 | input cp_req, |
| 5 | input [31:0] cp_insn, |
| 6 | output reg cp_ack, |
| 7 | output reg cp_busy, |
| 8 | input cp_rnw, |
| 9 | output reg [31:0] cp_read = 0, |
| 10 | input [31:0] cp_write); |
| 11 | |
| 12 | /* Terminal pretends to be cp5. */ |
| 13 | reg towrite = 0; |
| 14 | reg [7:0] data = 0; |
| 15 | reg [8:0] indata = 0; /* High bit is if data is present. */ |
| 16 | reg didread = 0; |
| 17 | |
| 18 | always @(*) |
| 19 | begin |
| 20 | towrite = 0; |
| 21 | data = 8'hxx; |
| 22 | cp_ack = 0; |
| 23 | cp_busy = 0; |
| 24 | cp_read = 0; |
| 25 | didread = 0; |
| 26 | if (cp_req && (cp_rnw == 0) && (cp_insn[27:24] == 4'b1110) && (cp_insn[19:16] == 4'b0000) && (cp_insn[11:8] == 4'h5)) |
| 27 | begin |
| 28 | towrite = 1; |
| 29 | data = cp_write[7:0]; |
| 30 | cp_ack = 1; |
| 31 | end else if (cp_req && (cp_rnw == 1) && (cp_insn[27:24] == 4'b1110) && (cp_insn[19:16] == 4'b0001) && (cp_insn[11:8] == 4'h5)) |
| 32 | begin |
| 33 | cp_read = {23'h0, indata[8:0]}; |
| 34 | cp_ack = 1; |
| 35 | didread = cp_insn[7:5] == 1; |
| 36 | end |
| 37 | end |
| 38 | `ifdef verilator |
| 39 | always @(posedge clk) |
| 40 | if (towrite) |
| 41 | $c("{extern void term_output(unsigned char d); term_output(",data,");}"); |
| 42 | else if (didread || !indata[8]) |
| 43 | indata = $c("({extern unsigned int term_input(); term_input();})"); |
| 44 | `endif |
| 45 | endmodule |