Add chip enable correctness for CellularRAM.
[firearm.git] / Issue.v
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1`include "ARM_Constants.v"
2
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3module Issue(
4 input clk,
09e28f01 5 input Nrst, /* XXX not used yet */
60cc768b 6
ae457ae9 7 input stall_1a, /* pipeline control */
8c1ba494 8 input flush_1a,
60cc768b 9
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10 input bubble_1a, /* stage inputs */
11 input [31:0] insn_1a,
12 input [31:0] pc_1a,
ae457ae9 13 input [31:0] cpsr_1a,
60cc768b 14
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15 output wire stall_0a, /* stage outputs */
16 output reg bubble_2a = 1,
17 output reg [31:0] pc_2a = 0,
18 output reg [31:0] insn_2a = 0
6595c4c8 19 /* XXX other? */
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20 );
21
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22`ifdef COPY_PASTA_FODDER
23 /* from page 2 of ARM7TDMIvE2.pdf */
a7297aa5 24 casex (insn_1a)
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25 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
26// `DECODE_ALU_MUL_LONG: /* Multiply long */
27 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
28 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
29 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
30 `DECODE_ALU_SWP: /* Atomic swap */
31 `DECODE_ALU_BX: /* Branch */
32 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
33 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
34 `DECODE_ALU: /* ALU */
35 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
36 `DECODE_LDRSTR: /* Single data transfer */
37 `DECODE_LDMSTM: /* Block data transfer */
38 `DECODE_BRANCH: /* Branch */
39 `DECODE_LDCSTC: /* Coprocessor data transfer */
40 `DECODE_CDP: /* Coprocessor data op */
41 `DECODE_MRCMCR: /* Coprocessor register transfer */
42 `DECODE_SWI: /* SWI */
43 default: /* X everything else out */
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44 endcase
45`endif
46
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47 /* Flag setting */
48 reg use_cpsr;
49 reg [15:0] use_regs;
50 reg def_cpsr;
51 reg [15:0] def_regs;
52
53 function [15:0] idxbit;
54 input [3:0] r;
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55 if (r == 15)
56 idxbit = 0;
57 else
58 idxbit = (16'b1) << r;
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59 endfunction
60
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61 wire [3:0] rn = insn_1a[19:16];
62 wire [3:0] rd = insn_1a[15:12];
63 wire [3:0] rs = insn_1a[11:8];
64 wire [3:0] rm = insn_1a[3:0];
65 wire [3:0] cond = insn_1a[31:28];
e216a134 66
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67 wire [3:0] rd_mul = insn_1a[19:16];
68 wire [3:0] rn_mul = insn_1a[15:12];
69 wire [3:0] rs_mul = insn_1a[11:8];
e216a134 70
a7297aa5 71 wire [3:0] alu_opc = insn_1a[24:21];
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72
73 function alu_is_logical;
74 input [3:0] op;
75
76 case (op)
77 `ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1;
78 default: alu_is_logical = 0;
79 endcase
80 endfunction
81
82 function alu_flags_only;
83 input [3:0] op;
84
85 case (op)
86 `ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1;
87 default: alu_flags_only = 0;
88 endcase
89 endfunction
90
91 function shift_requires_carry;
92 input [7:0] shift;
93
94 case(shift[1:0])
95 `SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0);
96 `SHIFT_LSR: shift_requires_carry = 0;
97 `SHIFT_ASR: shift_requires_carry = 0;
98 `SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0);
99 endcase
100 endfunction
101
e216a134 102 always @(*)
a7297aa5 103 casez (insn_1a)
6b8a01fa 104 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
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105 begin
106 use_cpsr = `COND_MATTERS(cond);
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107 use_regs = (insn_1a[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
108 def_cpsr = insn_1a[20] /* setcc */;
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109 def_regs = idxbit(rd_mul);
110 end
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111// `DECODE_ALU_MUL_LONG: /* Multiply long */
112 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
7aa8541b 113 begin
a7297aa5 114 use_cpsr = `COND_MATTERS(cond) || (insn_1a[22] == 0) /* Source = CPSR */;
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115 use_regs = 0;
116 def_cpsr = 0;
117 def_regs = idxbit(rd);
118 end
6b8a01fa 119 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
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120 begin
121 use_cpsr = `COND_MATTERS(cond);
122 use_regs = idxbit(rm);
123 def_cpsr = 1;
124 def_regs = 0;
125 end
6b8a01fa 126 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
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127 begin
128 use_cpsr = `COND_MATTERS(cond);
a7297aa5 129 use_regs = insn_1a[25] ? 0 : idxbit(rm);
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130 def_cpsr = 1;
131 def_regs = 0;
132 end
6b8a01fa 133 `DECODE_ALU_SWP: /* Atomic swap */
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134 begin
135 use_cpsr = `COND_MATTERS(cond);
136 use_regs = idxbit(rn) | idxbit(rm);
137 def_cpsr = 0;
138 def_regs = idxbit(rd);
139 end
6b8a01fa 140 `DECODE_ALU_BX: /* Branch */
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141 begin
142 use_cpsr = `COND_MATTERS(cond);
143 use_regs = idxbit(rm);
144 def_cpsr = 0; // don't care, we'll never get there
145 def_regs = 0;
146 end
6b8a01fa 147 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
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148 begin
149 use_cpsr = `COND_MATTERS(cond);
a7297aa5 150 use_regs = idxbit(rn) | idxbit(rm) | (insn_1a[20] /* L */ ? 0 : idxbit(rd));
7aa8541b 151 def_cpsr = 0;
a7297aa5 152 def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;
7aa8541b 153 end
6b8a01fa 154 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
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155 begin
156 use_cpsr = `COND_MATTERS(cond);
a7297aa5 157 use_regs = idxbit(rn) | (insn_1a[20] /* L */ ? 0 : idxbit(rd));
7aa8541b 158 def_cpsr = 0;
a7297aa5 159 def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;
7aa8541b 160 end
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161 `DECODE_ALU: /* ALU */
162 begin
a7297aa5 163 use_cpsr = `COND_MATTERS(cond) | (!insn_1a[25] /* I */ && shift_requires_carry(insn_1a[11:4]));
0ede28ef 164 use_regs =
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165 (insn_1a[25] /* I */ ? 0 :
166 (insn_1a[4] /* shift by reg */ ?
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167 (idxbit(rs) | idxbit(rm)) :
168 (idxbit(rm)))) |
169 (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
a7297aa5 170 def_cpsr = insn_1a[20] /* S */;
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171 def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
172 end
6b8a01fa 173 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
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174 begin
175 use_cpsr = 0;
176 use_regs = 0;
177 def_cpsr = 0;
178 def_regs = 0;
179 end
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180 `DECODE_LDRSTR:
181 begin
182 use_cpsr = `COND_MATTERS(cond);
a7297aa5 183 use_regs = idxbit(rn) | (insn_1a[25] /* I */ ? idxbit(rm) : 0) | (insn_1a[20] /* L */ ? 0 : idxbit(rd));
6b8a01fa 184 def_cpsr = 0;
a7297aa5 185 def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;
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186 end
187 `DECODE_LDMSTM: /* Block data transfer */
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188 begin
189 use_cpsr = `COND_MATTERS(cond);
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190 use_regs = idxbit(rn) | (insn_1a[20] /* L */ ? 0 : insn_1a[15:0]);
191 def_cpsr = insn_1a[22]; /* This is a superset of all cases, anyway. */
192 def_regs = (insn_1a[21] /* W */ ? idxbit(rn) : 0) | (insn_1a[20] /* L */ ? insn_1a[15:0] : 0);
7aa8541b 193 end
6b8a01fa 194 `DECODE_BRANCH: /* Branch */
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195 begin
196 use_cpsr = `COND_MATTERS(cond);
197 use_regs = 0;
198 def_cpsr = 0;
a7297aa5 199 def_regs = insn_1a[24] /* L */ ? (16'b1 << 14) : 0;
7aa8541b 200 end
6b8a01fa 201 `DECODE_LDCSTC: /* Coprocessor data transfer */
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202 begin
203 use_cpsr = `COND_MATTERS(cond);
204 use_regs = idxbit(rn);
205 def_cpsr = 0;
a7297aa5 206 def_regs = insn_1a[21] /* W */ ? idxbit(rn) : 0;
7aa8541b 207 end
6b8a01fa 208 `DECODE_CDP: /* Coprocessor data op */
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209 begin
210 use_cpsr = `COND_MATTERS(cond);
211 use_regs = 0;
212 def_cpsr = 0;
213 def_regs = 0;
214 end
6b8a01fa 215 `DECODE_MRCMCR: /* Coprocessor register transfer */
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216 begin
217 use_cpsr = `COND_MATTERS(cond);
a7297aa5 218 use_regs = insn_1a[20] /* L */ ? 0 : idxbit(rd);
7aa8541b 219 def_cpsr = 0;
a7297aa5 220 def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;
7aa8541b 221 end
6b8a01fa 222 `DECODE_SWI: /* SWI */
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223 begin
224 use_cpsr = `COND_MATTERS(cond);
225 use_regs = 0;
226 def_cpsr = 0;
227 def_regs = 0;
228 end
e216a134 229 default: /* X everything else out */
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230 begin
231 use_cpsr = 1'bx;
232 use_regs = 16'bxxxxxxxxxxxxxxxx;
233 def_cpsr = 1'bx;
234 def_regs = 16'bxxxxxxxxxxxxxxxx;
235 end
e216a134 236 endcase
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237
238 /* Condition checking logic */
ae457ae9 239 reg condition_met_1a;
ae281afd 240 always @(*)
a7297aa5 241 casez(insn_1a[31:28])
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242 `COND_EQ: condition_met_1a = cpsr_1a[`CPSR_Z];
243 `COND_NE: condition_met_1a = !cpsr_1a[`CPSR_Z];
244 `COND_CS: condition_met_1a = cpsr_1a[`CPSR_C];
245 `COND_CC: condition_met_1a = !cpsr_1a[`CPSR_C];
246 `COND_MI: condition_met_1a = cpsr_1a[`CPSR_N];
247 `COND_PL: condition_met_1a = !cpsr_1a[`CPSR_N];
248 `COND_VS: condition_met_1a = cpsr_1a[`CPSR_V];
249 `COND_VC: condition_met_1a = !cpsr_1a[`CPSR_V];
250 `COND_HI: condition_met_1a = cpsr_1a[`CPSR_C] && !cpsr_1a[`CPSR_Z];
251 `COND_LS: condition_met_1a = !cpsr_1a[`CPSR_C] || cpsr_1a[`CPSR_Z];
252 `COND_GE: condition_met_1a = cpsr_1a[`CPSR_N] == cpsr_1a[`CPSR_V];
253 `COND_LT: condition_met_1a = cpsr_1a[`CPSR_N] != cpsr_1a[`CPSR_V];
254 `COND_GT: condition_met_1a = !cpsr_1a[`CPSR_Z] && (cpsr_1a[`CPSR_N] == cpsr_1a[`CPSR_V]);
255 `COND_LE: condition_met_1a = cpsr_1a[`CPSR_Z] || (cpsr_1a[`CPSR_N] != cpsr_1a[`CPSR_V]);
256 `COND_AL: condition_met_1a = 1;
257 `COND_NV: condition_met_1a = 0;
258 default: condition_met_1a = 1'bx;
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259 endcase
260
261 /* Issue logic */
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262 /* Once it's hit writeback, it's hit the regfile via forwarding so you're done. */
263 reg cpsr_inflight_2a = 0, cpsr_inflight_3a = 0;
264 reg [15:0] regs_inflight_2a = 0, regs_inflight_3a = 0;
6595c4c8 265
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266 wire waiting_cpsr_1a = use_cpsr & (cpsr_inflight_2a | cpsr_inflight_3a);
267 wire waiting_regs_1a = |(use_regs & (regs_inflight_2a | regs_inflight_3a));
268 wire waiting_1a = waiting_cpsr_1a | waiting_regs_1a;
8c1ba494 269 assign stall_0a = (waiting_1a && !bubble_1a && !flush_1a) || stall_1a;
c4e2ac3b 270
8c1ba494 271 reg delayedflush_1a = 0;
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272 always @(posedge clk/* or negedge Nrst*/)
273 if (!Nrst)
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274 delayedflush_1a <= 0;
275 else if (flush_1a && stall_0a /* halp! I can't do it now, maybe later? */)
276 delayedflush_1a <= 1;
ae457ae9 277 else if (!stall_0a /* anything has been handled this time around */)
8c1ba494 278 delayedflush_1a <= 0;
a02d953f 279
6595c4c8 280 /* Actually do the issue. */
a4f724e6 281 always @(posedge clk or negedge Nrst)
6595c4c8 282 begin
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283 if (waiting_1a)
284 $display("ISSUE: Stalling instruction %08x because %d/%d", insn_1a, waiting_cpsr_1a, waiting_regs_1a);
149bcd1a 285
a4f724e6 286 if (!Nrst) begin
ae457ae9 287 bubble_2a <= 1;
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288 /*AUTORESET*/
289 // Beginning of autoreset for uninitialized flops
290 cpsr_inflight_2a <= 1'h0;
291 cpsr_inflight_3a <= 1'h0;
292 insn_2a <= 32'h0;
293 pc_2a <= 32'h0;
294 regs_inflight_2a <= 16'h0;
295 regs_inflight_3a <= 16'h0;
296 // End of automatics
ae457ae9 297 end else if (!stall_1a)
4ddc4b72 298 begin
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299 cpsr_inflight_3a <= cpsr_inflight_2a; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
300 cpsr_inflight_2a <= (waiting_1a || bubble_1a || !condition_met_1a) ? 0 : def_cpsr;
301 regs_inflight_3a <= regs_inflight_2a;
302 regs_inflight_2a <= (waiting_1a || bubble_1a || !condition_met_1a) ? 0 : def_regs;
4ddc4b72 303
8c1ba494 304 bubble_2a <= bubble_1a | waiting_1a | !condition_met_1a | flush_1a | delayedflush_1a;
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305 pc_2a <= pc_1a;
306 insn_2a <= insn_1a;
1c2e57dc 307 end
6595c4c8 308 end
60cc768b 309endmodule
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