Add chip enable correctness for CellularRAM.
[firearm.git] / CellularRAM.v
CommitLineData
1e7ff543
JW
1module CellularRAM(
2 input clk,
3 input [31:0] bus_addr,
4 output wire [31:0] bus_rdata,
5 input [31:0] bus_wdata,
6 input bus_rd,
7 input bus_wr,
8 output wire bus_ready,
9
10 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
11 inout wire [15:0] cr_DQ,
12 output wire [22:0] cr_A,
13 output wire st_nCE
14 );
15
16 /* This module is mapped in physical memory from 0x80000000 to
17 * 0x80FFFFFF. rdata and ready must be driven to zero if the
18 * address is not within the range of this module.
19 */
20 wire decode = bus_addr[31:24] == 8'h80;
21 assign cr_A = bus_addr[23:1];
22 reg [22:0] cr_A_1a = 23'h7FFFFF;
23 reg [22:0] cr_A_2a = 23'h7FFFFF;
24 wire active = (decode && (bus_rd || bus_wr));
25 reg active_1a = 0;
26 reg active_2a = 0;
27
28 always @(posedge clk)
29 begin
30 cr_A_1a <= cr_A;
31 cr_A_2a <= cr_A_1a;
32 active_1a <= active;
33 active_2a <= active_1a;
34 end
35
36 assign bus_rdata = (bus_rd && decode) ? {16'h0000, cr_DQ} : 32'h0;
37 assign cr_DQ = (bus_wr && decode) ? bus_wdata : 16'hzzzz;
38
39 assign bus_ready = active && active_1a && active_2a && (cr_A_1a == cr_A) && (cr_A_2a == cr_A);
40
41 assign st_nCE = 0;
42 assign cr_nADV = ~decode;
fccd83f9 43 assign cr_nCE = ~active;
1e7ff543
JW
44 assign cr_nOE = ~bus_rd;
45 assign cr_nWE = ~bus_wr;
46 assign cr_CRE = 0;
47 assign cr_nLB = 0;
48 assign cr_nUB = 0;
49 assign cr_CLK = 0;
50endmodule
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