Add chip enable correctness for CellularRAM.
[firearm.git] / BigBlockRAM.v
CommitLineData
90bdd4a8
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1module BigBlockRAM(
2 input clk,
3 input [31:0] bus_addr,
4 output wire [31:0] bus_rdata,
5 input [31:0] bus_wdata,
6 input bus_rd,
7 input bus_wr,
8 output wire bus_ready
9 );
10
11 /* This module is mapped in physical memory from 0x00000000 to
12 * 0x00800000. rdata and ready must be driven to zero if the
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13 * address is not within the range of this module. There also
14 * exists a shadow up at 0x80000000.
90bdd4a8 15 */
1e7ff543 16 wire decode = bus_addr[30:23] == 8'b0;
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17 wire [22:0] ramaddr = {bus_addr[22:2], 2'b0}; /* mask off lower two bits
18 * for word alignment */
19
20 reg [31:0] data [((8*1024*1024) / 4 - 1):0];
21
22 reg [31:0] temprdata = 0;
8b09558c 23 reg [22:0] lastread = 23'h7FFFFF;
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24 assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
25
26 assign bus_ready = decode &&
27 (bus_wr || (bus_rd && (lastread == ramaddr)));
28
29 initial
30 $readmemh("ram.hex", data);
31
32 always @(posedge clk)
33 begin
34 if (bus_wr && decode)
35 data[ramaddr[22:2]] = bus_wdata;
36
37 /* This is not allowed to be conditional -- stupid Xilinx
38 * blockram. */
39 temprdata <= data[ramaddr[22:2]];
40 lastread <= ramaddr;
41 end
42endmodule
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