[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	input flush,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,
	output reg [2:0] data_size,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	output reg cp_rnw,	/* 1 = read from CP, 0 = write to CP */
	input [31:0] cp_read,
	output reg [31:0] cp_write,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] outspsr = 32'hxxxxxxxx,
	output reg [31:0] outcpsr = 32'hxxxxxxxx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg [31:0] prevaddr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback;

	reg next_outbubble;	
	reg next_write_reg;
	reg [3:0] next_write_num;
	reg [31:0] next_write_data;

	reg [1:0] lsr_state = 2'b01, next_lsr_state;
	reg [31:0] align_s1, align_s2, align_rddata;

	reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
	reg [31:0] lsrh_rddata;
	reg [15:0] lsrh_rddata_s1;
	reg [7:0] lsrh_rddata_s2;

	reg [15:0] regs, next_regs;
	reg [2:0] lsm_state = 3'b001, next_lsm_state;
	reg [5:0] offset, prev_offset, offset_sel;

	reg [31:0] swp_oldval, next_swp_oldval;
	reg [1:0] swp_state = 2'b01, next_swp_state;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		regs <= next_regs;
		prev_reg <= cur_reg;
		prev_offset <= offset;
		prev_raddr <= raddr;
		outcpsr <= next_outcpsr;
		outspsr <= spsr;
		swp_state <= next_swp_state;
		lsm_state <= next_lsm_state;
		lsr_state <= next_lsr_state;
		lsrh_state <= next_lsrh_state;
		prevaddr <= addr;
	end
	
	reg delayedflush = 0;
	always @(posedge clk)
		if (flush && outstall /* halp! I can't do it now, maybe later? */)
			delayedflush <= 1;
		else if (!outstall /* anything has been handled this time around */)
			delayedflush <= 0;

	always @(*)
	begin
		addr = prevaddr;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		data_size = 3'bxxx;
		outstall = 1'b0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_outbubble = inbubble;
		next_regs = regs;
		cp_req = 1'b0;
		cp_rnw = 1'bx;
		cp_write = 32'hxxxxxxxx;
		offset = prev_offset;
		next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
		lsrh_rddata = 32'hxxxxxxxx;
		lsrh_rddata_s1 = 16'hxxxx;
		lsrh_rddata_s2 = 8'hxx;
		next_lsm_state = lsm_state;
		next_lsr_state = lsr_state;
		next_lsrh_state = lsrh_state;
		next_swp_oldval = swp_oldval;
		next_swp_state = swp_state;
		cur_reg = prev_reg;

		/* XXX shit not given about endianness */
		casez(insn)
		`DECODE_ALU_SWP: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			busaddr = {op0[31:2], 2'b0};
			data_size = insn[22] ? 3'b001 : 3'b100;
			case(swp_state)
			2'b01: begin
				rd_req = 1'b1;
				outstall = 1'b1;
				if(!rw_wait) begin
					next_swp_state = 2'b10;
					next_swp_oldval = rd_data;
				end
			end
			2'b10: begin
				wr_req = 1'b1;
				wr_data = insn[22] ? {4{op1[7:0]}} : op1;
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
				if(!rw_wait)
					next_swp_state = 2'b01;
			end
			default: begin end
			endcase
		end
		`DECODE_ALU_HDATA_REG,
		`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? op0 : addr; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			case(insn[6:5])
			2'b00: begin end /* swp */
			2'b01: begin /* unsigned half */
				wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
				data_size = 3'b010;
				lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
			end
			2'b10: begin /* signed byte */
				wr_data = {4{op2[7:0]}};
				data_size = 3'b001;
				lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
				lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
				lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
			end
			2'b11: begin /* signed half */
				wr_data = {2{op2[15:0]}};
				data_size = 3'b010;
				lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
			end
			endcase

			case(lsrh_state)
			2'b01: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				next_write_num = insn[15:12];
				next_write_data = lsrh_rddata;
				if(insn[20]) begin
					next_write_reg = 1'b1;
				end
				if(insn[21] | !insn[24]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsrh_state = 2'b10;
				end
			end
			2'b10: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsrh_state = 2'b10;
			end
			default: begin end
			endcase
		end
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? addr : op0; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
			/* select byte or word */
			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
			wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
			data_size = insn[22] ? 3'b001 : 3'b100;
			case(lsr_state)
			2'b01: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				if(insn[20]) begin
					next_write_data = align_rddata;
				end
				if(insn[21] | !insn[24]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsr_state = 2'b10;
				end
				$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
			end
			2'b10: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsr_state = 2'b01;
			end
			default: begin end
			endcase
		end
		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
		`DECODE_LDMSTM: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			data_size = 3'b100;
			case(lsm_state)
			3'b001: begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
				next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                            op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				outstall = 1'b1;
				next_lsm_state = 3'b010;
			end
			3'b010: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
				end

				if (rw_wait)
					offset = prev_offset;	/* whoops, do this one again */
				else
					offset = prev_offset + 6'h4;
				offset_sel = insn[24] ? offset : prev_offset;
				raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
				if(insn[20]) begin
					next_write_reg = !rw_wait;
					next_write_num = cur_reg;
					next_write_data = rd_data;
				end
				if (rw_wait) begin
					next_regs = regs;
					cur_reg = prev_reg;	/* whoops, do this one again */
				end

				st_read = cur_reg;
				wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
				busaddr = raddr;
				
				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);

				outstall = 1'b1;

				if(next_regs == 16'b0) begin
					next_lsm_state = 3'b100;
				end
			end
			3'b100: begin
				next_write_reg = insn[21] /* writeback */;
				next_write_num = insn[19:16];
				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				next_lsm_state = 3'b001;
				$display("LDMSTM: Stage 3: Writing back");
			end
			default: $stop;
			endcase
			$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
		end
		`DECODE_LDCSTC: if(!inbubble) begin
			$display("WARNING: Unimplemented LDCSTC");
		end
		`DECODE_CDP: if(!inbubble) begin
			cp_req = 1;
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				/* XXX undefined instruction trap */
				$display("WARNING: Possible CDP undefined instruction");
			end
		end
		`DECODE_MRCMCR: if(!inbubble) begin
			cp_req = 1;
			cp_rnw = insn[20] /* L */;
			if (insn[20] == 0 /* store to coprocessor */)
				cp_write = op0;
			else begin
				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = cp_read;
				end else
					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
			end
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
			end
			$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
		end
		default: begin end
		endcase
		
		if ((flush || delayedflush) && !outstall)
			next_outbubble = 1'b1;
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8	6
ab7ee9fc JW	7	input flush,
ab7ee9fc JW	8
b3bb2fb8 CL	9	/* bus interface */
	10	output reg [31:0] busaddr,
	11	output reg rd_req,
	12	output reg wr_req,
	13	input rw_wait,
	14	output reg [31:0] wr_data,
	15	input [31:0] rd_data,
9fc6c23c	16	output reg [2:0] data_size,
b3bb2fb8 CL	17
	18	/* regfile interface */
	19	output reg [3:0] st_read,
	20	input [31:0] st_data,
a02ca509	21
979f2bd7 JW	22	/* Coprocessor interface */
	23	output reg cp_req,
	24	input cp_ack,
	25	input cp_busy,
804dc0bc	26	output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c JW	27	input [31:0] cp_read,
43e4332c JW	28	output reg [31:0] cp_write,
979f2bd7	29
a02ca509 JW	30	/* stage inputs */
	31	input inbubble,
	32	input [31:0] pc,
	33	input [31:0] insn,
e68b2378 JW	34	input [31:0] op0,
e68b2378 JW	35	input [31:0] op1,
6d0f9d82	36	input [31:0] op2,
efd1aa13 CL	37	input [31:0] spsr,
efd1aa13 CL	38	input [31:0] cpsr,
a02ca509 JW	39	input write_reg,
	40	input [3:0] write_num,
	41	input [31:0] write_data,
b3bb2fb8	42
a02ca509 JW	43	/* outputs */
	44	output reg outstall,
	45	output reg outbubble,
b3bb2fb8	46	output reg [31:0] outpc,
a02ca509 JW	47	output reg [31:0] outinsn,
	48	output reg out_write_reg = 1'b0,
	49	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13	50	output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc JW	51	output reg [31:0] outspsr = 32'hxxxxxxxx,
ab7ee9fc JW	52	output reg [31:0] outcpsr = 32'hxxxxxxxx
a02ca509	53	);
b3bb2fb8	54
efd1aa13	55	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
666ceb03	56	reg [31:0] prevaddr;
e08b748a	57	reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43	58	reg next_writeback;
e08b748a	59
804dc0bc JW	60	reg next_outbubble;
	61	reg next_write_reg;
	62	reg [3:0] next_write_num;
	63	reg [31:0] next_write_data;
74d3729c	64
9a0d0e43	65	reg [1:0] lsr_state = 2'b01, next_lsr_state;
666ceb03 CL	66	reg [31:0] align_s1, align_s2, align_rddata;
	67
	68	reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
	69	reg [31:0] lsrh_rddata;
	70	reg [15:0] lsrh_rddata_s1;
	71	reg [7:0] lsrh_rddata_s2;
9a0d0e43	72
b783a475	73	reg [15:0] regs, next_regs;
9a0d0e43	74	reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f	75	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	76
9a0d0e43 CL	77	reg [31:0] swp_oldval, next_swp_oldval;
9a0d0e43 CL	78	reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509 JW	79
	80	always @(posedge clk)
	81	begin
	82	outpc <= pc;
	83	outinsn <= insn;
c65110a8 JW	84	outbubble <= next_outbubble;
	85	out_write_reg <= next_write_reg;
	86	out_write_num <= next_write_num;
	87	out_write_data <= next_write_data;
e68b2378	88	regs <= next_regs;
e08b748a	89	prev_reg <= cur_reg;
b114e03f CL	90	prev_offset <= offset;
b114e03f CL	91	prev_raddr <= raddr;
ab7ee9fc JW	92	outcpsr <= next_outcpsr;
ab7ee9fc JW	93	outspsr <= spsr;
9a0d0e43	94	swp_state <= next_swp_state;
666ceb03 CL	95	lsm_state <= next_lsm_state;
	96	lsr_state <= next_lsr_state;
	97	lsrh_state <= next_lsrh_state;
	98	prevaddr <= addr;
a02ca509	99	end
d73619a2 JW	100
	101	reg delayedflush = 0;
	102	always @(posedge clk)
	103	if (flush && outstall /* halp! I can't do it now, maybe later? */)
	104	delayedflush <= 1;
	105	else if (!outstall /* anything has been handled this time around */)
	106	delayedflush <= 0;
b3bb2fb8 CL	107
	108	always @(*)
	109	begin
666ceb03	110	addr = prevaddr;
b3bb2fb8 CL	111	raddr = 32'hxxxxxxxx;
	112	rd_req = 1'b0;
	113	wr_req = 1'b0;
	114	wr_data = 32'hxxxxxxxx;
	115	busaddr = 32'hxxxxxxxx;
2bcc55d5	116	data_size = 3'bxxx;
b3bb2fb8	117	outstall = 1'b0;
a02ca509 JW	118	next_write_reg = write_reg;
	119	next_write_num = write_num;
	120	next_write_data = write_data;
c65110a8	121	next_outbubble = inbubble;
9a0d0e43	122	next_regs = regs;
979f2bd7	123	cp_req = 1'b0;
43e4332c JW	124	cp_rnw = 1'bx;
43e4332c JW	125	cp_write = 32'hxxxxxxxx;
b114e03f	126	offset = prev_offset;
ab7ee9fc	127	next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
666ceb03	128	lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c CL	129	lsrh_rddata_s1 = 16'hxxxx;
9fc6c23c CL	130	lsrh_rddata_s2 = 8'hxx;
9a0d0e43 CL	131	next_lsm_state = lsm_state;
9a0d0e43 CL	132	next_lsr_state = lsr_state;
666ceb03	133	next_lsrh_state = lsrh_state;
9a0d0e43 CL	134	next_swp_oldval = swp_oldval;
	135	next_swp_state = swp_state;
	136	cur_reg = prev_reg;
9f082c0b	137
5989b2f5	138	/* XXX shit not given about endianness */
d73619a2	139	casez(insn)
5989b2f5 CL	140	`DECODE_ALU_SWP: if(!inbubble) begin
	141	outstall = rw_wait;
	142	next_outbubble = rw_wait;
	143	busaddr = {op0[31:2], 2'b0};
2bcc55d5	144	data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 CL	145	case(swp_state)
	146	2'b01: begin
	147	rd_req = 1'b1;
	148	outstall = 1'b1;
	149	if(!rw_wait) begin
	150	next_swp_state = 2'b10;
	151	next_swp_oldval = rd_data;
9a0d0e43	152	end
9a0d0e43	153	end
5989b2f5 CL	154	2'b10: begin
5989b2f5 CL	155	wr_req = 1'b1;
2bcc55d5	156	wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5 CL	157	next_write_reg = 1'b1;
5989b2f5 CL	158	next_write_num = insn[15:12];
2bcc55d5	159	next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5 CL	160	if(!rw_wait)
	161	next_swp_state = 2'b01;
	162	end
	163	default: begin end
	164	endcase
9a0d0e43	165	end
666ceb03 CL	166	`DECODE_ALU_HDATA_REG,
	167	`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
	168	next_outbubble = rw_wait;
	169	outstall = rw_wait;
	170	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	171	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	172	busaddr = raddr;
	173	/* rotate to correct position */
	174	case(insn[6:5])
	175	2'b00: begin end /* swp */
	176	2'b01: begin /* unsigned half */
	177	wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5	178	data_size = 3'b010;
666ceb03 CL	179	lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
	180	end
	181	2'b10: begin /* signed byte */
	182	wr_data = {4{op2[7:0]}};
2bcc55d5	183	data_size = 3'b001;
666ceb03 CL	184	lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
	185	lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
	186	lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
	187	end
	188	2'b11: begin /* signed half */
	189	wr_data = {2{op2[15:0]}};
2bcc55d5	190	data_size = 3'b010;
666ceb03 CL	191	lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
	192	end
	193	endcase
	194
	195	case(lsrh_state)
	196	2'b01: begin
	197	rd_req = insn[20];
	198	wr_req = ~insn[20];
	199	next_write_num = insn[15:12];
	200	next_write_data = lsrh_rddata;
	201	if(insn[20]) begin
	202	next_write_reg = 1'b1;
	203	end
	204	if(insn[21] \| !insn[24]) begin
	205	outstall = 1'b1;
	206	if(!rw_wait)
	207	next_lsrh_state = 2'b10;
	208	end
	209	end
	210	2'b10: begin
	211	next_write_reg = 1'b1;
	212	next_write_num = insn[19:16];
	213	next_write_data = addr;
	214	next_lsrh_state = 2'b10;
	215	end
	216	default: begin end
	217	endcase
	218	end
b3bb2fb8	219	`DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 CL	220	`DECODE_LDRSTR: if(!inbubble) begin
	221	next_outbubble = rw_wait;
	222	outstall = rw_wait;
	223	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be	224	raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03 CL	225	busaddr = raddr;
666ceb03 CL	226	/* rotate to correct position */
5989b2f5 CL	227	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	228	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	229	/* select byte or word */
	230	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
666ceb03	231	wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
2bcc55d5	232	data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 CL	233	case(lsr_state)
	234	2'b01: begin
	235	rd_req = insn[20];
	236	wr_req = ~insn[20];
666ceb03 CL	237	next_write_reg = 1'b1;
666ceb03 CL	238	next_write_num = insn[15:12];
5989b2f5	239	if(insn[20]) begin
5989b2f5	240	next_write_data = align_rddata;
a02ca509	241	end
666ceb03	242	if(insn[21] \| !insn[24]) begin
5989b2f5 CL	243	outstall = 1'b1;
	244	if(!rw_wait)
	245	next_lsr_state = 2'b10;
a02ca509	246	end
d73619a2	247	$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8	248	end
5989b2f5 CL	249	2'b10: begin
	250	next_write_reg = 1'b1;
	251	next_write_num = insn[19:16];
	252	next_write_data = addr;
feb2b5be	253	next_lsr_state = 2'b01;
5989b2f5 CL	254	end
	255	default: begin end
	256	endcase
b3bb2fb8	257	end
5989b2f5 CL	258	/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
5989b2f5 CL	259	`DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 CL	260	outstall = rw_wait;
9a0d0e43 CL	261	next_outbubble = rw_wait;
2bcc55d5	262	data_size = 3'b100;
9a0d0e43 CL	263	case(lsm_state)
9a0d0e43 CL	264	3'b001: begin
b114e03f CL	265	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
b114e03f CL	266	/** verilator can suck my dick */
b957d34d JW	267	$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
	268	next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	269	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f	270	offset = 6'b0;
9a0d0e43 CL	271	outstall = 1'b1;
9a0d0e43 CL	272	next_lsm_state = 3'b010;
e08b748a	273	end
9a0d0e43 CL	274	3'b010: begin
	275	rd_req = insn[20];
	276	wr_req = ~insn[20];
9f082c0b CL	277	casez(regs)
9f082c0b CL	278	16'b???????????????1: begin
e08b748a	279	cur_reg = 4'h0;
b114e03f	280	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	281	end
9f082c0b CL	282	16'b??????????????10: begin
e08b748a	283	cur_reg = 4'h1;
b114e03f	284	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	285	end
9f082c0b CL	286	16'b?????????????100: begin
e08b748a	287	cur_reg = 4'h2;
b114e03f	288	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	289	end
9f082c0b CL	290	16'b????????????1000: begin
e08b748a	291	cur_reg = 4'h3;
b114e03f	292	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	293	end
9f082c0b CL	294	16'b???????????10000: begin
e08b748a	295	cur_reg = 4'h4;
b114e03f	296	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	297	end
9f082c0b CL	298	16'b??????????100000: begin
e08b748a	299	cur_reg = 4'h5;
b114e03f	300	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	301	end
9f082c0b CL	302	16'b?????????1000000: begin
e08b748a	303	cur_reg = 4'h6;
b114e03f	304	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	305	end
9f082c0b CL	306	16'b????????10000000: begin
e08b748a	307	cur_reg = 4'h7;
b114e03f	308	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	309	end
9f082c0b CL	310	16'b???????100000000: begin
e08b748a	311	cur_reg = 4'h8;
b114e03f	312	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	313	end
9f082c0b CL	314	16'b??????1000000000: begin
e08b748a	315	cur_reg = 4'h9;
b114e03f	316	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	317	end
9f082c0b CL	318	16'b?????10000000000: begin
e08b748a	319	cur_reg = 4'hA;
b114e03f	320	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	321	end
9f082c0b CL	322	16'b????100000000000: begin
e08b748a	323	cur_reg = 4'hB;
b114e03f	324	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	325	end
9f082c0b CL	326	16'b???1000000000000: begin
e08b748a	327	cur_reg = 4'hC;
b114e03f	328	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	329	end
9f082c0b CL	330	16'b??10000000000000: begin
e08b748a	331	cur_reg = 4'hD;
b114e03f	332	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	333	end
9f082c0b CL	334	16'b?100000000000000: begin
e08b748a	335	cur_reg = 4'hE;
b114e03f	336	next_regs = {regs[15], 15'b0};
9f082c0b CL	337	end
9f082c0b CL	338	16'b1000000000000000: begin
e08b748a	339	cur_reg = 4'hF;
9f082c0b CL	340	next_regs = 16'b0;
	341	end
	342	default: begin
e08b748a CL	343	cur_reg = 4'hx;
e08b748a CL	344	next_regs = 16'b0;
9f082c0b CL	345	end
9f082c0b CL	346	endcase
b957d34d	347	cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13 CL	348	if(cur_reg == 4'hF && insn[22]) begin
	349	next_outcpsr = spsr;
	350	end
b114e03f	351
d73619a2 JW	352	if (rw_wait)
	353	offset = prev_offset; /* whoops, do this one again */
	354	else
9a0d0e43	355	offset = prev_offset + 6'h4;
d73619a2 JW	356	offset_sel = insn[24] ? offset : prev_offset;
	357	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	358	if(insn[20]) begin
	359	next_write_reg = !rw_wait;
	360	next_write_num = cur_reg;
	361	next_write_data = rd_data;
	362	end
	363	if (rw_wait) begin
	364	next_regs = regs;
	365	cur_reg = prev_reg; /* whoops, do this one again */
b114e03f CL	366	end
	367
	368	st_read = cur_reg;
b957d34d	369	wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03	370	busaddr = raddr;
b957d34d	371
d73619a2	372	$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43 CL	373
	374	outstall = 1'b1;
	375
	376	if(next_regs == 16'b0) begin
	377	next_lsm_state = 3'b100;
	378	end
	379	end
	380	3'b100: begin
b957d34d	381	next_write_reg = insn[21] /* writeback */;
9a0d0e43 CL	382	next_write_num = insn[19:16];
	383	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
	384	next_lsm_state = 3'b001;
d73619a2	385	$display("LDMSTM: Stage 3: Writing back");
b783a475	386	end
d73619a2	387	default: $stop;
9a0d0e43	388	endcase
d73619a2	389	$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8	390	end
5989b2f5	391	`DECODE_LDCSTC: if(!inbubble) begin
43e4332c JW	392	$display("WARNING: Unimplemented LDCSTC");
43e4332c JW	393	end
5989b2f5	394	`DECODE_CDP: if(!inbubble) begin
43e4332c JW	395	cp_req = 1;
	396	if (cp_busy) begin
	397	outstall = 1;
	398	next_outbubble = 1;
	399	end
	400	if (!cp_ack) begin
	401	/* XXX undefined instruction trap */
	402	$display("WARNING: Possible CDP undefined instruction");
	403	end
	404	end
5989b2f5	405	`DECODE_MRCMCR: if(!inbubble) begin
43e4332c JW	406	cp_req = 1;
	407	cp_rnw = insn[20] /* L */;
	408	if (insn[20] == 0 /* store to coprocessor */)
	409	cp_write = op0;
	410	else begin
d1d0eb8e JW	411	if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
	412	next_write_reg = 1'b1;
	413	next_write_num = insn[15:12];
	414	next_write_data = cp_read;
	415	end else
	416	next_outcpsr = {cp_read[31:28], cpsr[27:0]};
43e4332c JW	417	end
	418	if (cp_busy) begin
	419	outstall = 1;
	420	next_outbubble = 1;
	421	end
	422	if (!cp_ack) begin
838e283e	423	$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c	424	end
838e283e	425	$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c	426	end
b3bb2fb8 CL	427	default: begin end
b3bb2fb8 CL	428	endcase
d73619a2 JW	429
	430	if ((flush \|\| delayedflush) && !outstall)
	431	next_outbubble = 1'b1;
b3bb2fb8	432	end
b3bb2fb8	433	endmodule