Add fetch module
[firearm.git] / blockram.v
CommitLineData
2f8f0594
JW
1module BlockRAM(
2 input clk,
3 input [31:0] bus_addr,
4 output wire [31:0] bus_rdata,
5 input [31:0] bus_wdata,
6 input bus_rd,
7 input bus_wr,
8 output wire bus_ready
9 );
10
11 /* This module is mapped in physical memory from 0x00000000 to
12 * 0x00004000. rdata and ready must be driven to zero if the
13 * address is not within the range of this module.
14 */
15 wire decode = (addr & ~32'h00003FFF) == 32'h00004000;
16 wire [13:2] ramaddr = addr & 14'h3FFC; /* mask off lower two bits
17 * for word alignment */
18
19 reg [31:0] data [0:(16384 / 4 - 1)];
20
21 reg [31:0] temprdata;
22 reg [13:2] lastread;
23 assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
24
25 assign bus_ready = decode &&
26 (bus_wr || (bus_rd && (lastread == ramaddr)));
27
28 always @(posedge clk)
29 begin
30 if (bus_wr && decode)
31 data[ramaddr] <= bus_wdata;
32
33 /* This is not allowed to be conditional -- stupid Xilinx
34 * blockram. */
35 temprdata <= data[ramaddr];
36 lastread <= ramaddr;
37 end
38endmodule
This page took 0.020499 seconds and 4 git commands to generate.