do some first pass Execute wiring
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
bae77231
CL
3module Decode(
4 input clk,
be64a9df 5 input [31:0] insn,
bae77231 6 input [31:0] inpc,
821617bb 7 input [31:0] incpsr,
bae77231
CL
8 output reg [31:0] op0,
9 output reg [31:0] op1,
10 output reg [31:0] op2,
42c1e610 11 output reg carry,
bae77231 12
821617bb
JW
13 output [3:0] read_0,
14 output [3:0] read_1,
15 output [3:0] read_2,
16 input [31:0] rdata_0,
17 input [31:0] rdata_1,
18 input [31:0] rdata_2
bae77231
CL
19 );
20
21 wire [31:0] regs0, regs1, regs2, rpc;
42c1e610
JW
22 wire [31:0] op0_out, op1_out, op2_out;
23 wire carry_out;
bae77231
CL
24
25 /* shifter stuff */
26 wire [31:0] shift_oper;
27 wire [31:0] shift_res;
28 wire shift_cflag_out;
a0c8a75c 29 wire [31:0] rotate_res;
bae77231 30
821617bb
JW
31 assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
32 assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
33 assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231 34
e2c5d224
CL
35 IREALLYHATEARMSHIFT blowme(.insn(insn),
36 .operand(regs1),
37 .reg_amt(regs2),
38 .cflag_in(incpsr[`CPSR_C]),
39 .res(shift_res),
40 .cflag_out(shift_cflag_out));
41
a0c8a75c
CL
42 SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
43 .amt(insn[11:8]),
44 .res(rotate_res));
45
be64a9df
JW
46 always @(*)
47 casez (insn)
48 32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
49// 32'b????00001???????????????1001????, /* Multiply long */
50 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
51 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
52 32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
53 32'b????00010?00????????00001001????, /* Atomic swap */
0bc7ede9 54 32'b????000100101111111111110001????, /* Branch and exchange */
be64a9df
JW
55 32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
56 32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
57 32'b????011????????????????????1????, /* Undefined. I hate ARM */
58 32'b????01??????????????????????????, /* Single data transfer */
59 32'b????100?????????????????????????, /* Block data transfer */
60 32'b????101?????????????????????????, /* Branch */
61 32'b????110?????????????????????????, /* Coprocessor data transfer */
62 32'b????1110???????????????????0????, /* Coprocessor data op */
63 32'b????1110???????????????????1????, /* Coprocessor register transfer */
64 32'b????1111????????????????????????: /* SWI */
65 rpc = inpc - 8;
66 32'b????00??????????????????????????: /* ALU */
67 rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
68 default: /* X everything else out */
69 rpc = 32'hxxxxxxxx;
70 endcase
bae77231 71
326fd4c3
JW
72 always @(*) begin
73 read_0 = 4'hx;
74 read_1 = 4'hx;
75 read_2 = 4'hx;
76
0bc7ede9
JW
77 casez (insn)
78 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3 79 begin
0bc7ede9 80 read_0 = insn[15:12]; /* Rn */
326fd4c3
JW
81 read_1 = insn[3:0]; /* Rm */
82 read_2 = insn[11:8]; /* Rs */
83 end
0bc7ede9
JW
84// 32'b????00001???????????????1001????, /* Multiply long */
85// read_0 = insn[11:8]; /* Rn */
326fd4c3
JW
86// read_1 = insn[3:0]; /* Rm */
87// read_2 = 4'b0; /* anyus */
42c1e610
JW
88 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
89 begin end
0bc7ede9
JW
90 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
91 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
42c1e610 92 read_0 = insn[3:0]; /* Rm */
0bc7ede9 93 32'b????00??????????????????????????: /* ALU */
326fd4c3 94 begin
0bc7ede9 95 read_0 = insn[19:16]; /* Rn */
326fd4c3
JW
96 read_1 = insn[3:0]; /* Rm */
97 read_2 = insn[11:8]; /* Rs for shift */
98 end
0bc7ede9 99 32'b????00010?00????????00001001????: /* Atomic swap */
326fd4c3 100 begin
0bc7ede9 101 read_0 = insn[19:16]; /* Rn */
326fd4c3
JW
102 read_1 = insn[3:0]; /* Rm */
103 end
0bc7ede9
JW
104 32'b????000100101111111111110001????: /* Branch and exchange */
105 read_0 = insn[3:0]; /* Rn */
106 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
326fd4c3 107 begin
0bc7ede9 108 read_0 = insn[19:16];
326fd4c3
JW
109 read_1 = insn[3:0];
110 end
111 32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */
112 begin
0bc7ede9 113 read_0 = insn[19:16];
326fd4c3 114 end
0bc7ede9 115 32'b????011????????????????????1????: /* Undefined. I hate ARM */
326fd4c3 116 begin end
0bc7ede9 117 32'b????01??????????????????????????: /* Single data transfer */
326fd4c3 118 begin
0bc7ede9 119 read_0 = insn[19:16]; /* Rn */
326fd4c3
JW
120 read_1 = insn[3:0]; /* Rm */
121 end
0bc7ede9
JW
122 32'b????100?????????????????????????: /* Block data transfer */
123 read_0 = insn[19:16];
124 32'b????101?????????????????????????: /* Branch */
326fd4c3 125 begin end
0bc7ede9
JW
126 32'b????110?????????????????????????: /* Coprocessor data transfer */
127 read_0 = insn[19:16];
42c1e610
JW
128 32'b????1110???????????????????0????: /* Coprocessor data op */
129 begin end
130 32'b????1110???????????????????1????: /* Coprocessor register transfer */
131 read_0 = insn[15:12];
0bc7ede9 132 32'b????1111????????????????????????: /* SWI */
326fd4c3 133 begin end
b215c5ff 134 default:
326fd4c3 135 $display("Undecoded instruction");
b215c5ff 136 endcase
326fd4c3 137 end
b215c5ff 138
326fd4c3 139 always @(*) begin
42c1e610
JW
140 op0_out = 32'hxxxxxxxx;
141 op1_out = 32'hxxxxxxxx;
142 op2_out = 32'hxxxxxxxx;
143 carry_out = 1'bx;
be64a9df 144 casez (insn)
bae77231 145 32'b????000000??????????????1001????: begin /* Multiply */
42c1e610
JW
146 op0_out = regs0;
147 op1_out = regs1;
148 op2_out = regs2;
bae77231 149 end
b215c5ff
JW
150// 32'b????00001???????????????1001????: begin /* Multiply long */
151// op1_res = regs1;
152// end
bae77231 153 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
bae77231
CL
154 end
155 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
42c1e610 156 op0_out = regs0;
bae77231 157 end
42c1e610
JW
158 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
159 if(insn[25]) begin /* the constant case */
a0c8a75c 160 op0_out = rotate_res;
42c1e610
JW
161 end else begin
162 op0_out = regs0;
163 end
bae77231
CL
164 end
165 32'b????00??????????????????????????: begin /* ALU */
42c1e610 166 op0_out = regs0;
be64a9df 167 if(insn[25]) begin /* the constant case */
42c1e610 168 carry_out = incpsr[`CPSR_C];
a0c8a75c 169 op1_out = rotate_res;
bae77231 170 end else begin
42c1e610
JW
171 carry_out = shift_cflag_out;
172 op1_out = shift_res;
bae77231
CL
173 end
174 end
175 32'b????00010?00????????00001001????: begin /* Atomic swap */
42c1e610
JW
176 op0_out = regs0;
177 op1_out = regs1;
bae77231
CL
178 end
179 32'b????000100101111111111110001????: begin /* Branch and exchange */
42c1e610 180 op0_out = regs0;
bae77231
CL
181 end
182 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
42c1e610
JW
183 op0_out = regs0;
184 op1_out = regs1;
bae77231
CL
185 end
186 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
42c1e610
JW
187 op0_out = regs0;
188 op1_out = {24'b0, insn[11:8], insn[3:0]};
bae77231
CL
189 end
190 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
191 /* eat shit */
192 end
193 32'b????01??????????????????????????: begin /* Single data transfer */
42c1e610 194 op0_out = regs0;
be64a9df 195 if(insn[25]) begin
42c1e610
JW
196 op1_out = {20'b0, insn[11:0]};
197 carry_out = incpsr[`CPSR_C];
bae77231 198 end else begin
42c1e610
JW
199 op1_out = shift_res;
200 carry_out = shift_cflag_out;
bae77231
CL
201 end
202 end
203 32'b????100?????????????????????????: begin /* Block data transfer */
42c1e610
JW
204 op0_out = regs0;
205 op1_out = {16'b0, insn[15:0]};
bae77231
CL
206 end
207 32'b????101?????????????????????????: begin /* Branch */
42c1e610 208 op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231
CL
209 end
210 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
42c1e610
JW
211 op0_out = regs0;
212 op1_out = {24'b0, insn[7:0]};
bae77231
CL
213 end
214 32'b????1110???????????????????0????: begin /* Coprocessor data op */
bae77231
CL
215 end
216 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
42c1e610 217 op0_out = regs0;
bae77231
CL
218 end
219 32'b????1111????????????????????????: begin /* SWI */
bae77231 220 end
26049339 221 default: begin end
bae77231
CL
222 endcase
223 end
224
225 always @ (posedge clk) begin
42c1e610
JW
226 op0 <= op0_out; /* Rn - always */
227 op1 <= op1_out; /* 'operand 2' - Rm */
228 op2 <= op2_out; /* thirdedge - Rs */
229 carry <= carry_out;
bae77231
CL
230 end
231
232endmodule
233
e2c5d224 234module IREALLYHATEARMSHIFT(
bae77231
CL
235 input [31:0] insn,
236 input [31:0] operand,
237 input [31:0] reg_amt,
238 input cflag_in,
239 output [31:0] res,
240 output cflag_out
241);
bae77231 242 wire [5:0] shift_amt;
e2c5d224
CL
243 wire rshift_cout, is_arith, is_rot;
244 wire [31:0] rshift_res;
245
246 assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
247 : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231 248
e2c5d224
CL
249 SuckLessShifter biteme(.oper(operand),
250 .carryin(cflag_in),
251 .amt(shift_amt),
252 .is_arith(is_arith),
253 .is_rot(is_rot),
254 .res(rshift_res),
255 .carryout(rshift_cout));
bae77231 256
821617bb 257 always @(*)
e2c5d224
CL
258 case (insn[6:5])
259 `SHIFT_LSL: begin
e5fb7d86 260 /* meaningless */
e2c5d224
CL
261 is_rot = 1'b0;
262 is_arith = 1'b0;
26049339 263 end
e2c5d224
CL
264 `SHIFT_LSR: begin
265 is_rot = 1'b0;
266 is_arith = 1'b0;
267 end
268 `SHIFT_ASR: begin
269 is_rot = 1'b0;
270 is_arith = 1'b1;
271 end
272 `SHIFT_ROR: begin
273 is_rot = 1'b1;
274 is_arith = 1'b0;
275 end
276 endcase
277
821617bb 278 always @(*)
26049339 279 case (insn[6:5]) /* shift type */
e2c5d224
CL
280 `SHIFT_LSL:
281 {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231 282 `SHIFT_LSR: begin
e2c5d224
CL
283 res = rshift_res;
284 cflag_out = rshift_cout;
bae77231
CL
285 end
286 `SHIFT_ASR: begin
e2c5d224
CL
287 res = rshift_res;
288 cflag_out = rshift_cout;
bae77231
CL
289 end
290 `SHIFT_ROR: begin
e2c5d224 291 if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231
CL
292 res = {cflag_in, operand[31:1]};
293 cflag_out = operand[0];
e5fb7d86 294 end else begin
e2c5d224
CL
295 res = rshift_res;
296 cflag_out = rshift_cout;
bae77231
CL
297 end
298 end
26049339 299 endcase
bae77231 300endmodule
e2c5d224
CL
301
302module SuckLessShifter(
303 input [31:0] oper,
304 input carryin,
305 input [5:0] amt,
306 input is_arith,
307 input is_rot,
308 output [31:0] res,
309 output carryout
310);
311
312 wire [32:0] stage1, stage2, stage3, stage4, stage5;
313
e5fb7d86 314 wire pushbits = is_arith & oper[31];
e2c5d224
CL
315
316 /* do a barrel shift */
317 assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
5ad8b7c8
CL
318 assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
319 assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
320 assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
321 assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
322 assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;
e2c5d224
CL
323
324endmodule
a0c8a75c
CL
325
326module SuckLessRotator(
327 input [31:0] oper,
328 input [3:0] amt,
329 output [31:0] res
330);
331
332 wire [31:0] stage1, stage2, stage3;
333 assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
334 assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
335 assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
336 assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
337
338endmodule
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