ICache: Change cache_data to block RAM (yay!).
[firearm.git] / RegFile.v
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1module RegFile(
2 input clk,
a4f724e6 3 input Nrst,
821617bb 4 input [3:0] read_0,
f5f16509 5 output wire [31:0] rdata_0,
23c6da6c 6 input [3:0] read_1,
f5f16509 7 output wire [31:0] rdata_1,
23c6da6c 8 input [3:0] read_2,
f5f16509 9 output wire [31:0] rdata_2,
b3bb2fb8 10 input [3:0] read_3,
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11 output wire [31:0] rdata_3,
12 output wire [31:0] spsr,
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13 input write,
14 input [3:0] write_reg,
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15 input [31:0] write_data
16 );
17
18 reg [31:0] regfile [0:15];
a4f724e6 19 integer i;
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20
21 initial begin
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22 for (i = 0; i < 16; i = i + 1)
23 regfile[i] = 0;
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24 end
25
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26 assign rdata_0 = ((read_0 == write_reg) && write) ? write_data : regfile[read_0];
27 assign rdata_1 = ((read_1 == write_reg) && write) ? write_data : regfile[read_1];
28 assign rdata_2 = ((read_2 == write_reg) && write) ? write_data : regfile[read_2];
29 assign rdata_3 = ((read_3 == write_reg) && write) ? write_data : regfile[read_3];
30 assign spsr = regfile[4'hF];
23c6da6c 31
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32 always @(posedge clk or negedge Nrst)
33 if (!Nrst) begin
34 for (i = 0; i < 16; i = i + 1)
35 regfile[i] <= 0;
36 end else if (write)
ab7ee9fc 37 regfile[write_reg] <= write_data;
23c6da6c 38endmodule
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