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b3bb2fb8 CL |
1 | `include "ARM_Constants.v" |
2 | ||
3 | module Memory( | |
4 | input clk, | |
5 | input Nrst, | |
b3bb2fb8 CL |
6 | |
7 | /* bus interface */ | |
8 | output reg [31:0] busaddr, | |
9 | output reg rd_req, | |
10 | output reg wr_req, | |
11 | input rw_wait, | |
12 | output reg [31:0] wr_data, | |
13 | input [31:0] rd_data, | |
14 | ||
15 | /* regfile interface */ | |
16 | output reg [3:0] st_read, | |
17 | input [31:0] st_data, | |
a02ca509 JW |
18 | |
19 | /* stage inputs */ | |
20 | input inbubble, | |
21 | input [31:0] pc, | |
22 | input [31:0] insn, | |
e68b2378 JW |
23 | input [31:0] op0, |
24 | input [31:0] op1, | |
6d0f9d82 | 25 | input [31:0] op2, |
a02ca509 JW |
26 | input write_reg, |
27 | input [3:0] write_num, | |
28 | input [31:0] write_data, | |
b3bb2fb8 | 29 | |
a02ca509 JW |
30 | /* outputs */ |
31 | output reg outstall, | |
32 | output reg outbubble, | |
b3bb2fb8 | 33 | output reg [31:0] outpc, |
a02ca509 JW |
34 | output reg [31:0] outinsn, |
35 | output reg out_write_reg = 1'b0, | |
36 | output reg [3:0] out_write_num = 4'bxxxx, | |
37 | output reg [31:0] out_write_data = 32'hxxxxxxxx | |
38 | ); | |
b3bb2fb8 | 39 | |
c65110a8 JW |
40 | reg [31:0] addr, raddr; |
41 | reg next_notdone, next_inc_next; | |
74d3729c | 42 | reg [31:0] align_s1, align_s2, align_rddata; |
c65110a8 JW |
43 | |
44 | wire next_outbubble; | |
a02ca509 JW |
45 | wire next_write_reg; |
46 | wire [3:0] next_write_num; | |
47 | wire [31:0] next_write_data; | |
74d3729c | 48 | |
b783a475 | 49 | reg [15:0] regs, next_regs; |
74d3729c | 50 | |
b3bb2fb8 CL |
51 | reg notdone = 1'b0; |
52 | reg inc_next = 1'b0; | |
a02ca509 JW |
53 | |
54 | always @(posedge clk) | |
55 | begin | |
56 | outpc <= pc; | |
57 | outinsn <= insn; | |
c65110a8 JW |
58 | outbubble <= next_outbubble; |
59 | out_write_reg <= next_write_reg; | |
60 | out_write_num <= next_write_num; | |
61 | out_write_data <= next_write_data; | |
a02ca509 JW |
62 | notdone <= next_notdone; |
63 | inc_next <= next_inc_next; | |
e68b2378 | 64 | regs <= next_regs; |
a02ca509 | 65 | end |
b3bb2fb8 CL |
66 | |
67 | always @(*) | |
68 | begin | |
69 | addr = 32'hxxxxxxxx; | |
70 | raddr = 32'hxxxxxxxx; | |
71 | rd_req = 1'b0; | |
72 | wr_req = 1'b0; | |
73 | wr_data = 32'hxxxxxxxx; | |
74 | busaddr = 32'hxxxxxxxx; | |
75 | outstall = 1'b0; | |
74d3729c | 76 | next_notdone = 1'b0; |
a02ca509 JW |
77 | next_write_reg = write_reg; |
78 | next_write_num = write_num; | |
79 | next_write_data = write_data; | |
74d3729c | 80 | next_inc_next = 1'b0; |
c65110a8 | 81 | next_outbubble = inbubble; |
a02ca509 JW |
82 | outstall = 1'b0; |
83 | ||
b3bb2fb8 CL |
84 | casez(insn) |
85 | `DECODE_LDRSTR_UNDEFINED: begin end | |
86 | `DECODE_LDRSTR: begin | |
a02ca509 | 87 | if (!inbubble) begin |
c65110a8 | 88 | next_outbubble = rw_wait; |
a02ca509 JW |
89 | outstall = rw_wait | notdone; |
90 | ||
e68b2378 JW |
91 | addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ |
92 | raddr = insn[24] ? op0 : addr; /* pre/post increment */ | |
93 | busaddr = {raddr[31:2], 2'b0}; | |
a02ca509 JW |
94 | rd_req = insn[20]; |
95 | wr_req = ~insn[20]; | |
96 | ||
97 | /* rotate to correct position */ | |
98 | align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data; | |
99 | align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1; | |
100 | /* select byte or word */ | |
101 | align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2; | |
102 | ||
103 | if(!insn[20]) begin | |
6d0f9d82 | 104 | wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */ |
a02ca509 JW |
105 | end |
106 | else if(!inc_next) begin | |
107 | next_write_reg = 1'b1; | |
108 | next_write_num = insn[15:12]; | |
109 | next_write_data = align_rddata; | |
110 | next_inc_next = 1'b1; | |
111 | end | |
112 | else if(insn[21]) begin | |
113 | next_write_reg = 1'b1; | |
114 | next_write_num = insn[19:16]; | |
115 | next_write_data = addr; | |
116 | end | |
117 | next_notdone = rw_wait & insn[20] & insn[21]; | |
b3bb2fb8 | 118 | end |
b3bb2fb8 CL |
119 | end |
120 | `DECODE_LDMSTM: begin | |
b783a475 CL |
121 | busaddr = {op0[31:2], 2'b0}; |
122 | rd_req = insn[20]; | |
123 | wr_req = ~insn[20]; | |
124 | casez(regs) | |
125 | 16'b???????????????1: begin | |
126 | next_regs = regs; | |
127 | end | |
128 | 16'b??????????????10: begin | |
129 | end | |
130 | 16'b?????????????100: begin | |
131 | end | |
132 | 16'b????????????1000: begin | |
133 | end | |
134 | 16'b???????????10000: begin | |
135 | end | |
136 | 16'b??????????100000: begin | |
137 | end | |
138 | 16'b?????????1000000: begin | |
139 | end | |
140 | 16'b????????10000000: begin | |
141 | end | |
142 | 16'b???????100000000: begin | |
143 | end | |
144 | 16'b??????1000000000: begin | |
145 | end | |
146 | 16'b?????10000000000: begin | |
147 | end | |
148 | 16'b????100000000000: begin | |
149 | end | |
150 | 16'b???1000000000000: begin | |
151 | end | |
152 | 16'b??10000000000000: begin | |
153 | end | |
154 | 16'b?100000000000000: begin | |
155 | end | |
156 | 16'b1000000000000000: begin | |
157 | end | |
158 | default: begin | |
159 | next_inc_next = 1'b1; | |
160 | end | |
161 | endcase | |
b3bb2fb8 CL |
162 | end |
163 | default: begin end | |
164 | endcase | |
165 | end | |
b3bb2fb8 | 166 | endmodule |