Memory: Input renaming pass.
[firearm.git] / DCache.v
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1/* 16 cache entries, 64-byte long cache lines */
2
3module DCache(
4 input clk,
5
6 /* ARM core interface */
7 input [31:0] addr,
8 input rd_req,
9 input wr_req,
10 output reg rw_wait,
11 input [31:0] wr_data,
12 output reg [31:0] rd_data,
13
14 /* bus interface */
15 output wire bus_req,
16 input bus_ack,
17 output reg [31:0] bus_addr = 0,
18 input [31:0] bus_rdata,
19 output reg [31:0] bus_wdata,
20 output reg bus_rd = 0,
21 output reg bus_wr = 0,
22 input bus_ready);
23
24 /* [31 tag 10] [9 cache index 6] [5 data index 0]
25 * so the data index is 6 bits long
26 * so the cache index is 4 bits long
27 * so the tag is 22 bits long. c.c
28 */
29
30 reg cache_valid [15:0];
31 reg [21:0] cache_tags [15:0];
2b5c79c0 32 reg [31:0] cache_data [255:0 /* {line,word} */];
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33
34 integer i;
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35 initial
36 for (i = 0; i < 16; i = i + 1)
37 begin
38 cache_valid[i[3:0]] = 0;
39 cache_tags[i[3:0]] = 0;
40 end
41
42 wire [5:0] didx = addr[5:0];
43 wire [3:0] didx_word = didx[5:2];
44 wire [3:0] idx = addr[9:6];
45 wire [21:0] tag = addr[31:10];
46
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47 reg [31:0] prev_addr = 32'hFFFFFFFF;
48
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49 wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
50
2b5c79c0 51 wire [31:0] curdata = cache_data[{idx,didx_word}];
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52 always @(*) begin
53 rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
ac760abb 54 rd_data = curdata;
30066e06 55 if (!rw_wait && rd_req)
60c7a452 56 $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
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57 end
58
59 reg [3:0] cache_fill_pos = 0;
60 assign bus_req = (rd_req && !cache_hit) || wr_req;
61 always @(*)
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62 begin
63 bus_rd = 0;
64 bus_wr = 0;
65 bus_addr = 0;
66 bus_wdata = 0;
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67 if (rd_req && !cache_hit && bus_ack) begin
68 bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
69 bus_rd = 1;
70 end else if (wr_req && bus_ack) begin
e46e5a75 71 $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", addr, wr_data);
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72 bus_addr = addr;
73 bus_wr = 1;
74 bus_wdata = wr_data;
6060e535 75 end
0e3732b3 76 end
6060e535 77
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78 always @(posedge clk) begin
79 prev_addr <= {addr[31:6], 6'b0};
80 if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
81 cache_fill_pos <= 0;
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82 else if (rd_req && !cache_hit && bus_ready && bus_ack) begin /* Started the fill, and we have data. */
83 $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
84 cache_fill_pos <= cache_fill_pos + 1;
85 if (cache_fill_pos == 15) begin /* Done? */
86 cache_tags[idx] <= tag;
87 cache_valid[idx] <= 1;
88 end else
89 cache_valid[idx] <= 0;
90 end
91
92 /* Split this out because XST is kind of silly about this sort of thing. */
93 if ((rd_req && !cache_hit && bus_ready && bus_ack) || (wr_req && cache_hit))
94 cache_data[wr_req ? {idx,addr[5:2]} : {idx,cache_fill_pos}] <= wr_req ? wr_data : bus_rdata;
8b417b45 95 end
6060e535 96endmodule
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