DCache: Rename more internal wires.
[firearm.git] / DCache.v
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1/* 16 cache entries, 64-byte long cache lines */
2
3module DCache(
4 input clk,
5
6 /* ARM core interface */
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7 input [31:0] dc__addr_3a,
8 input dc__rd_req_3a,
9 input dc__wr_req_3a,
10 output reg dc__rw_wait_3a,
11 input [31:0] dc__wr_data_3a,
12 output reg [31:0] dc__rd_data_3a,
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13
14 /* bus interface */
15 output wire bus_req,
16 input bus_ack,
17 output reg [31:0] bus_addr = 0,
18 input [31:0] bus_rdata,
19 output reg [31:0] bus_wdata,
20 output reg bus_rd = 0,
21 output reg bus_wr = 0,
22 input bus_ready);
23
24 /* [31 tag 10] [9 cache index 6] [5 data index 0]
25 * so the data index is 6 bits long
26 * so the cache index is 4 bits long
27 * so the tag is 22 bits long. c.c
28 */
29
30 reg cache_valid [15:0];
31 reg [21:0] cache_tags [15:0];
2b5c79c0 32 reg [31:0] cache_data [255:0 /* {line,word} */];
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33
34 integer i;
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35 initial
36 for (i = 0; i < 16; i = i + 1)
37 begin
38 cache_valid[i[3:0]] = 0;
39 cache_tags[i[3:0]] = 0;
40 end
41
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42 wire [5:0] didx_3a = dc__addr_3a[5:0];
43 wire [3:0] didx_word_3a = didx_3a[5:2];
44 wire [3:0] idx_3a = dc__addr_3a[9:6];
45 wire [21:0] tag_3a = dc__addr_3a[31:10];
6060e535 46
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47 reg [31:0] prev_addr = 32'hFFFFFFFF;
48
a9f76b88 49 wire cache_hit_3a = cache_valid[idx_3a] && (cache_tags[idx_3a] == tag_3a);
6060e535 50
a9f76b88 51 wire [31:0] curdata_3a = cache_data[{idx_3a,didx_word_3a}];
6060e535 52 always @(*) begin
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53 dc__rw_wait_3a = (dc__rd_req_3a && !cache_hit_3a) || (dc__wr_req_3a && (!bus_ack || !bus_ready));
54 dc__rd_data_3a = curdata_3a;
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55 if (!dc__rw_wait_3a && dc__rd_req_3a)
56 $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", dc__addr_3a, dc__rd_data_3a);
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57 end
58
59 reg [3:0] cache_fill_pos = 0;
a9f76b88 60 assign bus_req = (dc__rd_req_3a && !cache_hit_3a) || dc__wr_req_3a;
6060e535 61 always @(*)
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62 begin
63 bus_rd = 0;
64 bus_wr = 0;
65 bus_addr = 0;
66 bus_wdata = 0;
a9f76b88 67 if (dc__rd_req_3a && !cache_hit_3a && bus_ack) begin
ed1fdafe 68 bus_addr = {dc__addr_3a[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
6060e535 69 bus_rd = 1;
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70 end else if (dc__wr_req_3a && bus_ack) begin
71 $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", dc__addr_3a, dc__wr_data_3a);
72 bus_addr = dc__addr_3a;
6060e535 73 bus_wr = 1;
ed1fdafe 74 bus_wdata = dc__wr_data_3a;
6060e535 75 end
0e3732b3 76 end
6060e535 77
8b417b45 78 always @(posedge clk) begin
ed1fdafe 79 prev_addr <= {dc__addr_3a[31:6], 6'b0};
a9f76b88 80 if (dc__rd_req_3a && (cache_fill_pos != 0) && ((prev_addr != {dc__addr_3a[31:6], 6'b0}) || cache_hit_3a)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
8b417b45 81 cache_fill_pos <= 0;
a9f76b88 82 else if (dc__rd_req_3a && !cache_hit_3a && bus_ready && bus_ack) begin /* Started the fill, and we have data. */
ed1fdafe 83 $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", dc__addr_3a, bus_addr, bus_rdata, bus_req, bus_ack);
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84 cache_fill_pos <= cache_fill_pos + 1;
85 if (cache_fill_pos == 15) begin /* Done? */
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86 cache_tags[idx_3a] <= tag_3a;
87 cache_valid[idx_3a] <= 1;
2b5c79c0 88 end else
a9f76b88 89 cache_valid[idx_3a] <= 0;
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90 end
91
92 /* Split this out because XST is kind of silly about this sort of thing. */
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93 if ((dc__rd_req_3a && !cache_hit_3a && bus_ready && bus_ack) || (dc__wr_req_3a && cache_hit_3a))
94 cache_data[dc__wr_req_3a ? {idx_3a,dc__addr_3a[5:2]} : {idx_3a,cache_fill_pos}] <= dc__wr_req_3a ? dc__wr_data_3a : bus_rdata;
8b417b45 95 end
6060e535 96endmodule
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