ICache: Add instrumentation.
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
bae77231
CL
3module Decode(
4 input clk,
e74c7936 5 input stall,
be64a9df 6 input [31:0] insn,
bae77231 7 input [31:0] inpc,
821617bb 8 input [31:0] incpsr,
cb0428b6 9 input [31:0] inspsr,
bae77231
CL
10 output reg [31:0] op0,
11 output reg [31:0] op1,
12 output reg [31:0] op2,
42c1e610 13 output reg carry,
ab7ee9fc 14 output reg [31:0] outcpsr,
cb0428b6 15 output reg [31:0] outspsr,
bae77231 16
fbe84cc1
JW
17 output reg [3:0] read_0,
18 output reg [3:0] read_1,
19 output reg [3:0] read_2,
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JW
20 input [31:0] rdata_0,
21 input [31:0] rdata_1,
22 input [31:0] rdata_2
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CL
23 );
24
fbe84cc1
JW
25 wire [31:0] regs0, regs1, regs2;
26 reg [31:0] rpc;
27 reg [31:0] op0_out, op1_out, op2_out;
28 reg carry_out;
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CL
29
30 /* shifter stuff */
31 wire [31:0] shift_oper;
32 wire [31:0] shift_res;
33 wire shift_cflag_out;
a0c8a75c 34 wire [31:0] rotate_res;
bae77231 35
821617bb
JW
36 assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
37 assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
38 assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231 39
96f7e6e1
JW
40 IREALLYHATEARMSHIFT shift(.insn(insn),
41 .operand(regs1),
42 .reg_amt(regs2),
43 .cflag_in(incpsr[`CPSR_C]),
44 .res(shift_res),
45 .cflag_out(shift_cflag_out));
e2c5d224 46
a0c8a75c
CL
47 SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
48 .amt(insn[11:8]),
49 .res(rotate_res));
50
be64a9df
JW
51 always @(*)
52 casez (insn)
2c523f8a
JW
53 `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
54// `DECODE_ALU_MUL_LONG, /* Multiply long */
55 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
56 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
57 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
58 `DECODE_ALU_SWP, /* Atomic swap */
59 `DECODE_ALU_BX, /* Branch and exchange */
60 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
61 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
62 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
63 `DECODE_LDRSTR, /* Single data transfer */
64 `DECODE_LDMSTM, /* Block data transfer */
65 `DECODE_BRANCH, /* Branch */
66 `DECODE_LDCSTC, /* Coprocessor data transfer */
67 `DECODE_CDP, /* Coprocessor data op */
2c523f8a 68 `DECODE_SWI: /* SWI */
b3bb2fb8 69 rpc = inpc + 8;
04d95cf5
JW
70 `DECODE_MRCMCR: /* Coprocessor register transfer */
71 rpc = inpc + 12;
2c523f8a 72 `DECODE_ALU: /* ALU */
b3bb2fb8 73 rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
2c523f8a 74 default: /* X everything else out */
be64a9df
JW
75 rpc = 32'hxxxxxxxx;
76 endcase
96f7e6e1 77
326fd4c3
JW
78 always @(*) begin
79 read_0 = 4'hx;
80 read_1 = 4'hx;
81 read_2 = 4'hx;
82
96f7e6e1
JW
83 op0_out = 32'hxxxxxxxx;
84 op1_out = 32'hxxxxxxxx;
85 op2_out = 32'hxxxxxxxx;
86 carry_out = 1'bx;
87
0bc7ede9 88 casez (insn)
2c523f8a 89 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3 90 begin
0bc7ede9 91 read_0 = insn[15:12]; /* Rn */
326fd4c3
JW
92 read_1 = insn[3:0]; /* Rm */
93 read_2 = insn[11:8]; /* Rs */
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JW
94
95 op0_out = regs0;
96 op1_out = regs1;
97 op2_out = regs2;
326fd4c3 98 end
2c523f8a 99// `DECODE_ALU_MUL_LONG: /* Multiply long */
96f7e6e1 100// begin
0bc7ede9 101// read_0 = insn[11:8]; /* Rn */
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102// read_1 = insn[3:0]; /* Rm */
103// read_2 = 4'b0; /* anyus */
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104//
105// op1_res = regs1;
106// end
2c523f8a 107 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610 108 begin end
96f7e6e1
JW
109 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
110 begin
111 read_0 = insn[3:0]; /* Rm */
112
113 op0_out = regs0;
114 end
2c523f8a 115 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
96f7e6e1 116 begin
42c1e610 117 read_0 = insn[3:0]; /* Rm */
96f7e6e1
JW
118
119 if(insn[25]) begin /* the constant case */
120 op0_out = rotate_res;
121 end else begin
122 op0_out = regs0;
123 end
124 end
2c523f8a 125 `DECODE_ALU_SWP: /* Atomic swap */
326fd4c3 126 begin
0bc7ede9 127 read_0 = insn[19:16]; /* Rn */
326fd4c3 128 read_1 = insn[3:0]; /* Rm */
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JW
129
130 op0_out = regs0;
131 op1_out = regs1;
326fd4c3 132 end
2c523f8a 133 `DECODE_ALU_BX: /* Branch and exchange */
96f7e6e1 134 begin
0bc7ede9 135 read_0 = insn[3:0]; /* Rn */
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JW
136
137 op0_out = regs0;
138 end
2c523f8a 139 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3 140 begin
0bc7ede9 141 read_0 = insn[19:16];
326fd4c3 142 read_1 = insn[3:0];
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CL
143 read_2 = insn[15:12];
144
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145 op0_out = regs0;
146 op1_out = regs1;
778ef14f 147 op2_out = regs2;
326fd4c3 148 end
2c523f8a 149 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3 150 begin
0bc7ede9 151 read_0 = insn[19:16];
778ef14f 152 read_1 = insn[15:12];
96f7e6e1
JW
153
154 op0_out = regs0;
155 op1_out = {24'b0, insn[11:8], insn[3:0]};
778ef14f 156 op2_out = regs1;
326fd4c3 157 end
2c523f8a
JW
158 `DECODE_ALU: /* ALU */
159 begin
160 read_0 = insn[19:16]; /* Rn */
161 read_1 = insn[3:0]; /* Rm */
162 read_2 = insn[11:8]; /* Rs for shift */
96f7e6e1 163
2c523f8a
JW
164 op0_out = regs0;
165 if(insn[25]) begin /* the constant case */
166 carry_out = incpsr[`CPSR_C];
167 op1_out = rotate_res;
168 end else begin
169 carry_out = shift_cflag_out;
170 op1_out = shift_res;
171 end
172 end
96f7e6e1
JW
173 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
174 begin
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CL
175 /* eat shit */
176 end
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177 `DECODE_LDRSTR: /* Single data transfer */
178 begin
179 read_0 = insn[19:16]; /* Rn */
180 read_1 = insn[3:0]; /* Rm */
6d0f9d82 181 read_2 = insn[15:12];
96f7e6e1 182
42c1e610 183 op0_out = regs0;
be64a9df 184 if(insn[25]) begin
42c1e610
JW
185 op1_out = {20'b0, insn[11:0]};
186 carry_out = incpsr[`CPSR_C];
bae77231 187 end else begin
42c1e610
JW
188 op1_out = shift_res;
189 carry_out = shift_cflag_out;
bae77231 190 end
6d0f9d82 191 op2_out = regs2;
bae77231 192 end
96f7e6e1
JW
193 `DECODE_LDMSTM: /* Block data transfer */
194 begin
195 read_0 = insn[19:16];
196
42c1e610
JW
197 op0_out = regs0;
198 op1_out = {16'b0, insn[15:0]};
bae77231 199 end
96f7e6e1
JW
200 `DECODE_BRANCH: /* Branch */
201 begin
42c1e610 202 op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231 203 end
96f7e6e1
JW
204 `DECODE_LDCSTC: /* Coprocessor data transfer */
205 begin
206 read_0 = insn[19:16];
207
42c1e610
JW
208 op0_out = regs0;
209 op1_out = {24'b0, insn[7:0]};
bae77231 210 end
96f7e6e1
JW
211 `DECODE_CDP: /* Coprocessor data op */
212 begin
bae77231 213 end
96f7e6e1
JW
214 `DECODE_MRCMCR: /* Coprocessor register transfer */
215 begin
216 read_0 = insn[15:12];
217
42c1e610 218 op0_out = regs0;
bae77231 219 end
96f7e6e1
JW
220 `DECODE_SWI: /* SWI */
221 begin
bae77231 222 end
96f7e6e1
JW
223 default:
224 $display("Undecoded instruction");
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CL
225 endcase
226 end
227
96f7e6e1 228
bae77231 229 always @ (posedge clk) begin
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JW
230 if (!stall)
231 begin
232 op0 <= op0_out; /* Rn - always */
233 op1 <= op1_out; /* 'operand 2' - Rm */
234 op2 <= op2_out; /* thirdedge - Rs */
235 carry <= carry_out;
236 outcpsr <= incpsr;
237 outspsr <= inspsr;
238 end
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CL
239 end
240
241endmodule
242
e2c5d224 243module IREALLYHATEARMSHIFT(
bae77231
CL
244 input [31:0] insn,
245 input [31:0] operand,
246 input [31:0] reg_amt,
247 input cflag_in,
fbe84cc1
JW
248 output reg [31:0] res,
249 output reg cflag_out
bae77231 250);
bae77231 251 wire [5:0] shift_amt;
f61f8d6f
JW
252 reg is_arith, is_rot;
253 wire rshift_cout;
254 wire [31:0] rshift_res;
e2c5d224
CL
255
256 assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
257 : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231 258
96f7e6e1 259 SuckLessShifter barrel(.oper(operand),
e2c5d224
CL
260 .carryin(cflag_in),
261 .amt(shift_amt),
262 .is_arith(is_arith),
263 .is_rot(is_rot),
264 .res(rshift_res),
265 .carryout(rshift_cout));
bae77231 266
821617bb 267 always @(*)
e2c5d224
CL
268 case (insn[6:5])
269 `SHIFT_LSL: begin
e5fb7d86 270 /* meaningless */
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CL
271 is_rot = 1'b0;
272 is_arith = 1'b0;
26049339 273 end
e2c5d224
CL
274 `SHIFT_LSR: begin
275 is_rot = 1'b0;
276 is_arith = 1'b0;
277 end
278 `SHIFT_ASR: begin
279 is_rot = 1'b0;
280 is_arith = 1'b1;
281 end
282 `SHIFT_ROR: begin
283 is_rot = 1'b1;
284 is_arith = 1'b0;
285 end
286 endcase
287
821617bb 288 always @(*)
26049339 289 case (insn[6:5]) /* shift type */
e2c5d224
CL
290 `SHIFT_LSL:
291 {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231 292 `SHIFT_LSR: begin
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CL
293 res = rshift_res;
294 cflag_out = rshift_cout;
bae77231
CL
295 end
296 `SHIFT_ASR: begin
e2c5d224
CL
297 res = rshift_res;
298 cflag_out = rshift_cout;
bae77231
CL
299 end
300 `SHIFT_ROR: begin
e2c5d224 301 if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
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302 res = {cflag_in, operand[31:1]};
303 cflag_out = operand[0];
e5fb7d86 304 end else begin
e2c5d224
CL
305 res = rshift_res;
306 cflag_out = rshift_cout;
bae77231
CL
307 end
308 end
26049339 309 endcase
bae77231 310endmodule
e2c5d224
CL
311
312module SuckLessShifter(
313 input [31:0] oper,
314 input carryin,
315 input [5:0] amt,
316 input is_arith,
317 input is_rot,
f61f8d6f
JW
318 output wire [31:0] res,
319 output wire carryout
e2c5d224
CL
320);
321
322 wire [32:0] stage1, stage2, stage3, stage4, stage5;
323
e5fb7d86 324 wire pushbits = is_arith & oper[31];
e2c5d224
CL
325
326 /* do a barrel shift */
327 assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10
CL
328 assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
329 assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
330 assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
331 assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
332 assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224
CL
333
334endmodule
a0c8a75c
CL
335
336module SuckLessRotator(
337 input [31:0] oper,
338 input [3:0] amt,
f61f8d6f 339 output wire [31:0] res
a0c8a75c
CL
340);
341
342 wire [31:0] stage1, stage2, stage3;
343 assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
344 assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
345 assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
346 assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
347
348endmodule
96f7e6e1 349
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