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Commit | Line | Data |
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b3bb2fb8 CL |
1 | `include "ARM_Constants.v" |
2 | ||
3 | module Memory( | |
4 | input clk, | |
5 | input Nrst, | |
b3bb2fb8 CL |
6 | |
7 | /* bus interface */ | |
8 | output reg [31:0] busaddr, | |
9 | output reg rd_req, | |
10 | output reg wr_req, | |
11 | input rw_wait, | |
12 | output reg [31:0] wr_data, | |
13 | input [31:0] rd_data, | |
14 | ||
15 | /* regfile interface */ | |
16 | output reg [3:0] st_read, | |
17 | input [31:0] st_data, | |
a02ca509 | 18 | |
979f2bd7 JW |
19 | /* Coprocessor interface */ |
20 | output reg cp_req, | |
21 | input cp_ack, | |
22 | input cp_busy, | |
23 | ||
a02ca509 JW |
24 | /* stage inputs */ |
25 | input inbubble, | |
26 | input [31:0] pc, | |
27 | input [31:0] insn, | |
e68b2378 JW |
28 | input [31:0] op0, |
29 | input [31:0] op1, | |
6d0f9d82 | 30 | input [31:0] op2, |
a02ca509 JW |
31 | input write_reg, |
32 | input [3:0] write_num, | |
33 | input [31:0] write_data, | |
b3bb2fb8 | 34 | |
a02ca509 JW |
35 | /* outputs */ |
36 | output reg outstall, | |
37 | output reg outbubble, | |
b3bb2fb8 | 38 | output reg [31:0] outpc, |
a02ca509 JW |
39 | output reg [31:0] outinsn, |
40 | output reg out_write_reg = 1'b0, | |
41 | output reg [3:0] out_write_num = 4'bxxxx, | |
42 | output reg [31:0] out_write_data = 32'hxxxxxxxx | |
43 | ); | |
b3bb2fb8 | 44 | |
5bcb3b7e | 45 | reg [31:0] addr, raddr, next_regdata; |
e08b748a | 46 | reg [3:0] next_regsel, cur_reg, prev_reg; |
74d3729c CL |
47 | reg next_writeback, next_notdone, next_inc_next; |
48 | reg [31:0] align_s1, align_s2, align_rddata; | |
e08b748a | 49 | |
c65110a8 | 50 | wire next_outbubble; |
a02ca509 JW |
51 | wire next_write_reg; |
52 | wire [3:0] next_write_num; | |
53 | wire [31:0] next_write_data; | |
74d3729c | 54 | |
b783a475 | 55 | reg [15:0] regs, next_regs; |
e08b748a | 56 | reg started = 1'b0, next_started; |
74d3729c | 57 | |
b3bb2fb8 CL |
58 | reg notdone = 1'b0; |
59 | reg inc_next = 1'b0; | |
a02ca509 JW |
60 | |
61 | always @(posedge clk) | |
62 | begin | |
63 | outpc <= pc; | |
64 | outinsn <= insn; | |
c65110a8 JW |
65 | outbubble <= next_outbubble; |
66 | out_write_reg <= next_write_reg; | |
67 | out_write_num <= next_write_num; | |
68 | out_write_data <= next_write_data; | |
a02ca509 JW |
69 | notdone <= next_notdone; |
70 | inc_next <= next_inc_next; | |
e68b2378 | 71 | regs <= next_regs; |
e08b748a CL |
72 | prev_reg <= cur_reg; |
73 | started <= next_started; | |
a02ca509 | 74 | end |
b3bb2fb8 CL |
75 | |
76 | always @(*) | |
77 | begin | |
78 | addr = 32'hxxxxxxxx; | |
79 | raddr = 32'hxxxxxxxx; | |
80 | rd_req = 1'b0; | |
81 | wr_req = 1'b0; | |
82 | wr_data = 32'hxxxxxxxx; | |
83 | busaddr = 32'hxxxxxxxx; | |
84 | outstall = 1'b0; | |
74d3729c | 85 | next_notdone = 1'b0; |
a02ca509 JW |
86 | next_write_reg = write_reg; |
87 | next_write_num = write_num; | |
88 | next_write_data = write_data; | |
74d3729c | 89 | next_inc_next = 1'b0; |
c65110a8 | 90 | next_outbubble = inbubble; |
a02ca509 | 91 | outstall = 1'b0; |
9f082c0b | 92 | next_regs = 16'b0; |
e08b748a | 93 | next_started = started; |
979f2bd7 | 94 | cp_req = 1'b0; |
9f082c0b | 95 | |
b3bb2fb8 CL |
96 | casez(insn) |
97 | `DECODE_LDRSTR_UNDEFINED: begin end | |
98 | `DECODE_LDRSTR: begin | |
a02ca509 | 99 | if (!inbubble) begin |
c65110a8 | 100 | next_outbubble = rw_wait; |
a02ca509 JW |
101 | outstall = rw_wait | notdone; |
102 | ||
e68b2378 JW |
103 | addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ |
104 | raddr = insn[24] ? op0 : addr; /* pre/post increment */ | |
105 | busaddr = {raddr[31:2], 2'b0}; | |
a02ca509 JW |
106 | rd_req = insn[20]; |
107 | wr_req = ~insn[20]; | |
108 | ||
109 | /* rotate to correct position */ | |
110 | align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data; | |
111 | align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1; | |
112 | /* select byte or word */ | |
113 | align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2; | |
114 | ||
115 | if(!insn[20]) begin | |
6d0f9d82 | 116 | wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */ |
a02ca509 JW |
117 | end |
118 | else if(!inc_next) begin | |
119 | next_write_reg = 1'b1; | |
120 | next_write_num = insn[15:12]; | |
121 | next_write_data = align_rddata; | |
122 | next_inc_next = 1'b1; | |
123 | end | |
124 | else if(insn[21]) begin | |
125 | next_write_reg = 1'b1; | |
126 | next_write_num = insn[19:16]; | |
127 | next_write_data = addr; | |
128 | end | |
129 | next_notdone = rw_wait & insn[20] & insn[21]; | |
b3bb2fb8 | 130 | end |
b3bb2fb8 CL |
131 | end |
132 | `DECODE_LDMSTM: begin | |
b783a475 CL |
133 | rd_req = insn[20]; |
134 | wr_req = ~insn[20]; | |
e08b748a CL |
135 | if(!started) begin |
136 | next_regs = op1[15:0]; | |
137 | next_started = 1'b1; | |
138 | end | |
139 | else if(inc_next) begin | |
140 | if(insn[21]) begin | |
141 | next_write_reg = 1'b1; | |
142 | next_write_num = insn[19:16]; | |
143 | next_write_data = op0; | |
144 | end | |
145 | next_started = 1'b0; | |
b783a475 | 146 | end |
e08b748a | 147 | else if(rw_wait) begin |
9f082c0b | 148 | next_regs = regs; |
e08b748a CL |
149 | cur_reg = prev_reg; |
150 | end | |
9f082c0b CL |
151 | else begin |
152 | casez(regs) | |
153 | 16'b???????????????1: begin | |
e08b748a | 154 | cur_reg = 4'h0; |
9f082c0b CL |
155 | next_regs = regs & 16'b1111111111111110; |
156 | end | |
157 | 16'b??????????????10: begin | |
e08b748a | 158 | cur_reg = 4'h1; |
9f082c0b CL |
159 | next_regs = regs & 16'b1111111111111100; |
160 | end | |
161 | 16'b?????????????100: begin | |
e08b748a | 162 | cur_reg = 4'h2; |
9f082c0b CL |
163 | next_regs = regs & 16'b1111111111111000; |
164 | end | |
165 | 16'b????????????1000: begin | |
e08b748a | 166 | cur_reg = 4'h3; |
9f082c0b CL |
167 | next_regs = regs & 16'b1111111111110000; |
168 | end | |
169 | 16'b???????????10000: begin | |
e08b748a | 170 | cur_reg = 4'h4; |
9f082c0b CL |
171 | next_regs = regs & 16'b1111111111100000; |
172 | end | |
173 | 16'b??????????100000: begin | |
e08b748a | 174 | cur_reg = 4'h5; |
9f082c0b CL |
175 | next_regs = regs & 16'b1111111111000000; |
176 | end | |
177 | 16'b?????????1000000: begin | |
e08b748a | 178 | cur_reg = 4'h6; |
9f082c0b CL |
179 | next_regs = regs & 16'b1111111110000000; |
180 | end | |
181 | 16'b????????10000000: begin | |
e08b748a | 182 | cur_reg = 4'h7; |
9f082c0b CL |
183 | next_regs = regs & 16'b1111111100000000; |
184 | end | |
185 | 16'b???????100000000: begin | |
e08b748a | 186 | cur_reg = 4'h8; |
9f082c0b CL |
187 | next_regs = regs & 16'b1111111000000000; |
188 | end | |
189 | 16'b??????1000000000: begin | |
e08b748a | 190 | cur_reg = 4'h9; |
9f082c0b CL |
191 | next_regs = regs & 16'b1111110000000000; |
192 | end | |
193 | 16'b?????10000000000: begin | |
e08b748a | 194 | cur_reg = 4'hA; |
9f082c0b CL |
195 | next_regs = regs & 16'b1111100000000000; |
196 | end | |
197 | 16'b????100000000000: begin | |
e08b748a | 198 | cur_reg = 4'hB; |
9f082c0b CL |
199 | next_regs = regs & 16'b1111000000000000; |
200 | end | |
201 | 16'b???1000000000000: begin | |
e08b748a | 202 | cur_reg = 4'hC; |
9f082c0b CL |
203 | next_regs = regs & 16'b1110000000000000; |
204 | end | |
205 | 16'b??10000000000000: begin | |
e08b748a | 206 | cur_reg = 4'hD; |
9f082c0b CL |
207 | next_regs = regs & 16'b1100000000000000; |
208 | end | |
209 | 16'b?100000000000000: begin | |
e08b748a | 210 | cur_reg = 4'hE; |
9f082c0b CL |
211 | next_regs = regs & 16'b1000000000000000; |
212 | end | |
213 | 16'b1000000000000000: begin | |
e08b748a | 214 | cur_reg = 4'hF; |
9f082c0b CL |
215 | next_regs = 16'b0; |
216 | end | |
217 | default: begin | |
e08b748a CL |
218 | cur_reg = 4'hx; |
219 | next_regs = 16'b0; | |
9f082c0b CL |
220 | end |
221 | endcase | |
222 | next_inc_next = next_regs == 16'b0; | |
e08b748a | 223 | next_notdone = ~next_inc_next | (rw_wait & insn[20] & insn[21]); |
b783a475 | 224 | end |
b3bb2fb8 CL |
225 | end |
226 | default: begin end | |
227 | endcase | |
228 | end | |
b3bb2fb8 | 229 | endmodule |