Memory: Change offset latch in LDM so that there is no flutter if DCache cannot get...
[firearm.git] / DCache.v
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1/* 16 cache entries, 64-byte long cache lines */
2
3module DCache(
4 input clk,
5
6 /* ARM core interface */
7 input [31:0] addr,
8 input rd_req,
9 input wr_req,
10 output reg rw_wait,
11 input [31:0] wr_data,
12 output reg [31:0] rd_data,
13
14 /* bus interface */
15 output wire bus_req,
16 input bus_ack,
17 output reg [31:0] bus_addr = 0,
18 input [31:0] bus_rdata,
19 output reg [31:0] bus_wdata,
20 output reg bus_rd = 0,
21 output reg bus_wr = 0,
22 input bus_ready);
23
24 /* [31 tag 10] [9 cache index 6] [5 data index 0]
25 * so the data index is 6 bits long
26 * so the cache index is 4 bits long
27 * so the tag is 22 bits long. c.c
28 */
29
30 reg cache_valid [15:0];
31 reg [21:0] cache_tags [15:0];
32 reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
33
34 reg [4:0] i;
35 initial
36 for (i = 0; i < 16; i = i + 1)
37 begin
38 cache_valid[i[3:0]] = 0;
39 cache_tags[i[3:0]] = 0;
40 end
41
42 wire [5:0] didx = addr[5:0];
43 wire [3:0] didx_word = didx[5:2];
44 wire [3:0] idx = addr[9:6];
45 wire [21:0] tag = addr[31:10];
46
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47 reg [31:0] prev_addr = 32'hFFFFFFFF;
48
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49 wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
50
51 always @(*) begin
52 rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
53 rd_data = cache_data[idx][didx_word];
30066e06 54 if (!rw_wait && rd_req)
60c7a452 55 $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
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56 end
57
58 reg [3:0] cache_fill_pos = 0;
59 assign bus_req = (rd_req && !cache_hit) || wr_req;
60 always @(*)
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61 begin
62 bus_rd = 0;
63 bus_wr = 0;
64 bus_addr = 0;
65 bus_wdata = 0;
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66 if (rd_req && !cache_hit && bus_ack) begin
67 bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
68 bus_rd = 1;
69 end else if (wr_req && bus_ack) begin
30066e06 70 $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x, wait %d", addr, wr_data, rw_wait);
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71 bus_addr = addr;
72 bus_wr = 1;
73 bus_wdata = wr_data;
6060e535 74 end
0e3732b3 75 end
6060e535 76
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77 always @(posedge clk) begin
78 prev_addr <= {addr[31:6], 6'b0};
79 if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
80 cache_fill_pos <= 0;
81 else if (rd_req && !cache_hit) begin
52fd78ff 82 if (bus_ready && bus_ack) begin /* Started the fill, and we have data. */
d91508c2 83 $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
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84 cache_data[idx][cache_fill_pos] <= bus_rdata;
85 cache_fill_pos <= cache_fill_pos + 1;
86 if (cache_fill_pos == 15) begin /* Done? */
87 cache_tags[idx] <= tag;
88 cache_valid[idx] <= 1;
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89 end else
90 cache_valid[idx] <= 0;
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91 end
92 end else if (wr_req && cache_hit)
93 cache_data[idx][addr[5:2]] = wr_data;
8b417b45 94 end
6060e535 95endmodule
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