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[firearm.git] / ICache.v
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1/* 16 cache entries, 64-byte long cache lines */
2
3module ICache(
4 input clk,
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5
6 /* ARM core interface */
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7 input [31:0] rd_addr,
8 input rd_req,
9 output reg rd_wait,
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10 output reg [31:0] rd_data,
11
12 /* bus interface */
13 output reg bus_req,
14 input bus_ack,
15 output reg [31:0] bus_addr,
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16 input [31:0] bus_rdata,
17 output wire [31:0] bus_wdata,
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18 output reg bus_rd,
19 output wire bus_wr,
20 input bus_ready);
21
22 assign bus_wr = 0;
cb1e103e 23 assign bus_wdata = 0;
7e757d70 24
f83818d5 25 /* [31 tag 10] [9 cache index 6] [5 data index 0]
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26 * so the data index is 6 bits long
27 * so the cache index is 4 bits long
f83818d5 28 * so the tag is 22 bits long. c.c
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29 */
30
31 reg cache_valid [15:0];
f83818d5 32 reg [21:0] cache_tags [15:0];
28c904cc 33 reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
7e757d70 34
cb1e103e 35 reg [4:0] i;
7e757d70 36 initial
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37 for (i = 0; i < 16; i = i + 1)
38 cache_valid[i[3:0]] = 0;
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39
40 wire [5:0] rd_didx = rd_addr[5:0];
41 wire [3:0] rd_didx_word = rd_didx[5:2];
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42 wire [3:0] rd_idx = rd_addr[9:6];
43 wire [21:0] rd_tag = rd_addr[31:10];
7e757d70 44
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45 wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
46
7e757d70 47 always @(*) begin /* XXX does this work nowadays? */
327f45ff 48 rd_wait = rd_req && !cache_hit;
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49 rd_data = cache_data[rd_idx][rd_didx_word];
50 end
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51
52 reg [3:0] cache_fill_pos = 0;
45fa96c0 53 assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
28c904cc 54 always @(*)
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55 if (rd_req && !cache_hit && bus_ack) begin
56 bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
57 bus_rd = 1;
327f45ff 58 end else begin
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59 bus_addr = 0;
60 bus_rd = 0;
61 end
62
63 always @(posedge clk)
64 if (rd_req && !cache_hit) begin
65 if (bus_ready) begin /* Started the fill, and we have data. */
45fa96c0 66 cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
327f45ff 67 cache_fill_pos <= cache_fill_pos + 1;
cb1e103e 68 if (cache_fill_pos == 15) begin /* Done? */
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69 cache_tags[rd_idx] <= rd_tag;
70 cache_valid[rd_idx] <= 1;
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71 end
72 end
c808669d 73 end
7e757d70 74endmodule
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