[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	input flush,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,
	output reg [2:0] data_size,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	output reg cp_rnw,	/* 1 = read from CP, 0 = write to CP */
	input [31:0] cp_read,
	output reg [31:0] cp_write,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input cpsrup,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] outspsr = 32'hxxxxxxxx,
	output reg [31:0] outcpsr = 32'hxxxxxxxx,
	output reg outcpsrup = 1'hx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg next_outcpsrup;
	reg [31:0] prevaddr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback;

	reg next_outbubble;	
	reg next_write_reg;
	reg [3:0] next_write_num;
	reg [31:0] next_write_data;

	reg [2:0] lsr_state = 3'b001, next_lsr_state;
	reg [31:0] align_s1, align_s2, align_rddata;

	reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
	reg [31:0] lsrh_rddata;
	reg [15:0] lsrh_rddata_s1;
	reg [7:0] lsrh_rddata_s2;

	reg [15:0] regs, next_regs;
	reg [3:0] lsm_state = 4'b0001, next_lsm_state;
	reg [5:0] offset, prev_offset, offset_sel;

	reg [31:0] swp_oldval, next_swp_oldval;
	reg [1:0] swp_state = 2'b01, next_swp_state;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		regs <= next_regs;
		prev_reg <= cur_reg;
		if (!rw_wait)
			prev_offset <= offset;
		prev_raddr <= raddr;
		outcpsr <= next_outcpsr;
		outspsr <= spsr;
		outcpsrup <= next_outcpsrup;
		swp_state <= next_swp_state;
		lsm_state <= next_lsm_state;
		lsr_state <= next_lsr_state;
		lsrh_state <= next_lsrh_state;
		prevaddr <= addr;
	end
	
	reg delayedflush = 0;
	always @(posedge clk)
		if (flush && outstall /* halp! I can't do it now, maybe later? */)
			delayedflush <= 1;
		else if (!outstall /* anything has been handled this time around */)
			delayedflush <= 0;

	always @(*)
	begin
		addr = prevaddr;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		data_size = 3'bxxx;
		outstall = 1'b0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_outbubble = inbubble;
		next_regs = regs;
		cp_req = 1'b0;
		cp_rnw = 1'bx;
		cp_write = 32'hxxxxxxxx;
		offset = prev_offset;
		next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
		next_outcpsrup = cpsrup;
		lsrh_rddata = 32'hxxxxxxxx;
		lsrh_rddata_s1 = 16'hxxxx;
		lsrh_rddata_s2 = 8'hxx;
		next_lsm_state = lsm_state;
		next_lsr_state = lsr_state;
		next_lsrh_state = lsrh_state;
		next_swp_oldval = swp_oldval;
		next_swp_state = swp_state;
		cur_reg = prev_reg;

		/* XXX shit not given about endianness */
		casez(insn)
		`DECODE_ALU_SWP: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			busaddr = {op0[31:2], 2'b0};
			data_size = insn[22] ? 3'b001 : 3'b100;
			case(swp_state)
			2'b01: begin
				rd_req = 1'b1;
				outstall = 1'b1;
				if(!rw_wait) begin
					next_swp_state = 2'b10;
					next_swp_oldval = rd_data;
				end
				$display("SWP: read stage");
			end
			2'b10: begin
				wr_req = 1'b1;
				wr_data = insn[22] ? {4{op1[7:0]}} : op1;
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
				if(!rw_wait)
					next_swp_state = 2'b01;
				$display("SWP: write stage");
			end
			default: begin end
			endcase
		end
		`DECODE_ALU_MULT: begin end
		`DECODE_ALU_HDATA_REG,
		`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? op0 : addr; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			case(insn[6:5])
			2'b00: begin end /* swp */
			2'b01: begin /* unsigned half */
				wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
				data_size = 3'b010;
				lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
			end
			2'b10: begin /* signed byte */
				wr_data = {4{op2[7:0]}};
				data_size = 3'b001;
				lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
				lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
				lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
			end
			2'b11: begin /* signed half */
				wr_data = {2{op2[15:0]}};
				data_size = 3'b010;
				lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
			end
			endcase

			case(lsrh_state)
			3'b001: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				next_write_num = insn[15:12];
				next_write_data = lsrh_rddata;
				if(insn[20]) begin
					next_write_reg = 1'b1;
				end
				if(insn[21] | !insn[24]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsrh_state = 3'b010;
				end
				$display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
			end
			3'b010: begin
				next_outbubble = 1'b0;
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsrh_state = 3'b100;
			end
			3'b100: begin
				outstall = 0;
				next_lsrh_state = 3'b001;
			end
			default: begin end
			endcase
			
			if ((lsrh_state == 3'b001) && flush) begin	/* Reject it. */
				outstall = 1'b0;
				next_lsrh_state = 3'b001;
			end
		end
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? addr : op0; /* pre/post increment */
			busaddr = raddr;
			/* rotate to correct position */
			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
			/* select byte or word */
			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
			wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
			data_size = insn[22] ? 3'b001 : 3'b100;
			case(lsr_state)
			3'b001: begin
				rd_req = insn[20] /* L */;
				wr_req = ~insn[20] /* L */;
				next_write_reg = insn[20] /* L */;
				next_write_num = insn[15:12];
				if(insn[20] /* L */) begin
					next_write_data = align_rddata;
				end
				if(insn[21] /* W */ | !insn[24] /* P */) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsr_state = 3'b010;
				end
				$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
			end
			3'b010: begin
				outstall = 1;
				next_outbubble = 0;
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsr_state = 3'b100;
			end
			3'b100: begin
				outstall = 0;
				next_lsr_state = 3'b001;
			end
			default: begin end
			endcase
			
			if ((lsr_state == 3'b001) && flush) begin	/* Reject it. */
				outstall = 1'b0;
				next_lsr_state = 3'b001;
			end
		end
		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
		`DECODE_LDMSTM: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			data_size = 3'b100;
			case(lsm_state)
			4'b0001: begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
				next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                            op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				outstall = 1'b1;
				next_lsm_state = 4'b0010;
			end
			4'b0010: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
					next_outcpsrup = 1;
				end

				offset = prev_offset + 6'h4;
				offset_sel = insn[24] ? offset : prev_offset;
				raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
				if(insn[20]) begin
					next_write_reg = !rw_wait;
					next_write_num = cur_reg;
					next_write_data = rd_data;
				end
				if (rw_wait) begin
					next_regs = regs;
					cur_reg = prev_reg;	/* whoops, do this one again */
				end

				st_read = cur_reg;
				wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
				busaddr = raddr;
				
				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);

				outstall = 1'b1;

				if(next_regs == 16'b0) begin
					next_lsm_state = 4'b0100;
				end
			end
			4'b0100: begin
				outstall = 1;
				next_outbubble = 0;
				next_write_reg = insn[21] /* writeback */;
				next_write_num = insn[19:16];
				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				next_lsm_state = 4'b1000;
				$display("LDMSTM: Stage 3: Writing back");
			end
			4'b1000: begin
				outstall = 0;
				next_lsm_state = 4'b0001;
			end
			default: $stop;
			endcase
			if ((lsm_state == 4'b0001) && flush) begin	/* Reject it. */
				outstall = 1'b0;
				next_lsm_state = 4'b0001;
			end
			$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
		end
		`DECODE_LDCSTC: if(!inbubble) begin
			$display("WARNING: Unimplemented LDCSTC");
		end
		`DECODE_CDP: if(!inbubble) begin
			cp_req = 1;
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				/* XXX undefined instruction trap */
				$display("WARNING: Possible CDP undefined instruction");
			end
		end
		`DECODE_MRCMCR: if(!inbubble) begin
			cp_req = 1;
			cp_rnw = insn[20] /* L */;
			if (insn[20] == 0 /* store to coprocessor */)
				cp_write = op0;
			else begin
				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = cp_read;
				end else begin
					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
					next_outcpsrup = 1;
				end
			end
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
			end
			$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
		end
		default: begin end
		endcase
		
		if ((flush || delayedflush) && !outstall)
			next_outbubble = 1'b1;
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8	6
ab7ee9fc JW	7	input flush,
ab7ee9fc JW	8
b3bb2fb8 CL	9	/* bus interface */
	10	output reg [31:0] busaddr,
	11	output reg rd_req,
	12	output reg wr_req,
	13	input rw_wait,
	14	output reg [31:0] wr_data,
	15	input [31:0] rd_data,
9fc6c23c	16	output reg [2:0] data_size,
b3bb2fb8 CL	17
	18	/* regfile interface */
	19	output reg [3:0] st_read,
	20	input [31:0] st_data,
a02ca509	21
979f2bd7 JW	22	/* Coprocessor interface */
	23	output reg cp_req,
	24	input cp_ack,
	25	input cp_busy,
804dc0bc	26	output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c JW	27	input [31:0] cp_read,
43e4332c JW	28	output reg [31:0] cp_write,
979f2bd7	29
a02ca509 JW	30	/* stage inputs */
	31	input inbubble,
	32	input [31:0] pc,
	33	input [31:0] insn,
e68b2378 JW	34	input [31:0] op0,
e68b2378 JW	35	input [31:0] op1,
6d0f9d82	36	input [31:0] op2,
efd1aa13 CL	37	input [31:0] spsr,
efd1aa13 CL	38	input [31:0] cpsr,
fdecc897	39	input cpsrup,
a02ca509 JW	40	input write_reg,
	41	input [3:0] write_num,
	42	input [31:0] write_data,
b3bb2fb8	43
a02ca509 JW	44	/* outputs */
	45	output reg outstall,
	46	output reg outbubble,
b3bb2fb8	47	output reg [31:0] outpc,
a02ca509 JW	48	output reg [31:0] outinsn,
	49	output reg out_write_reg = 1'b0,
	50	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13	51	output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc	52	output reg [31:0] outspsr = 32'hxxxxxxxx,
fdecc897 JW	53	output reg [31:0] outcpsr = 32'hxxxxxxxx,
fdecc897 JW	54	output reg outcpsrup = 1'hx
a02ca509	55	);
b3bb2fb8	56
efd1aa13	57	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
fdecc897	58	reg next_outcpsrup;
666ceb03	59	reg [31:0] prevaddr;
e08b748a	60	reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43	61	reg next_writeback;
e08b748a	62
804dc0bc JW	63	reg next_outbubble;
	64	reg next_write_reg;
	65	reg [3:0] next_write_num;
	66	reg [31:0] next_write_data;
74d3729c	67
4d7253f1	68	reg [2:0] lsr_state = 3'b001, next_lsr_state;
666ceb03 CL	69	reg [31:0] align_s1, align_s2, align_rddata;
666ceb03 CL	70
4d7253f1	71	reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
666ceb03 CL	72	reg [31:0] lsrh_rddata;
	73	reg [15:0] lsrh_rddata_s1;
	74	reg [7:0] lsrh_rddata_s2;
9a0d0e43	75
b783a475	76	reg [15:0] regs, next_regs;
4d7253f1	77	reg [3:0] lsm_state = 4'b0001, next_lsm_state;
b114e03f	78	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	79
9a0d0e43 CL	80	reg [31:0] swp_oldval, next_swp_oldval;
9a0d0e43 CL	81	reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509 JW	82
	83	always @(posedge clk)
	84	begin
	85	outpc <= pc;
	86	outinsn <= insn;
c65110a8 JW	87	outbubble <= next_outbubble;
	88	out_write_reg <= next_write_reg;
	89	out_write_num <= next_write_num;
	90	out_write_data <= next_write_data;
e68b2378	91	regs <= next_regs;
e08b748a	92	prev_reg <= cur_reg;
95704fd3 JW	93	if (!rw_wait)
95704fd3 JW	94	prev_offset <= offset;
b114e03f	95	prev_raddr <= raddr;
ab7ee9fc JW	96	outcpsr <= next_outcpsr;
ab7ee9fc JW	97	outspsr <= spsr;
fdecc897	98	outcpsrup <= next_outcpsrup;
9a0d0e43	99	swp_state <= next_swp_state;
666ceb03 CL	100	lsm_state <= next_lsm_state;
	101	lsr_state <= next_lsr_state;
	102	lsrh_state <= next_lsrh_state;
	103	prevaddr <= addr;
a02ca509	104	end
d73619a2 JW	105
	106	reg delayedflush = 0;
	107	always @(posedge clk)
	108	if (flush && outstall /* halp! I can't do it now, maybe later? */)
	109	delayedflush <= 1;
	110	else if (!outstall /* anything has been handled this time around */)
	111	delayedflush <= 0;
b3bb2fb8 CL	112
	113	always @(*)
	114	begin
666ceb03	115	addr = prevaddr;
b3bb2fb8 CL	116	raddr = 32'hxxxxxxxx;
	117	rd_req = 1'b0;
	118	wr_req = 1'b0;
	119	wr_data = 32'hxxxxxxxx;
	120	busaddr = 32'hxxxxxxxx;
2bcc55d5	121	data_size = 3'bxxx;
b3bb2fb8	122	outstall = 1'b0;
a02ca509 JW	123	next_write_reg = write_reg;
	124	next_write_num = write_num;
	125	next_write_data = write_data;
c65110a8	126	next_outbubble = inbubble;
9a0d0e43	127	next_regs = regs;
979f2bd7	128	cp_req = 1'b0;
43e4332c JW	129	cp_rnw = 1'bx;
43e4332c JW	130	cp_write = 32'hxxxxxxxx;
b114e03f	131	offset = prev_offset;
4d7253f1	132	next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
fdecc897	133	next_outcpsrup = cpsrup;
666ceb03	134	lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c CL	135	lsrh_rddata_s1 = 16'hxxxx;
9fc6c23c CL	136	lsrh_rddata_s2 = 8'hxx;
9a0d0e43 CL	137	next_lsm_state = lsm_state;
9a0d0e43 CL	138	next_lsr_state = lsr_state;
666ceb03	139	next_lsrh_state = lsrh_state;
9a0d0e43 CL	140	next_swp_oldval = swp_oldval;
	141	next_swp_state = swp_state;
	142	cur_reg = prev_reg;
9f082c0b	143
5989b2f5	144	/* XXX shit not given about endianness */
d73619a2	145	casez(insn)
5989b2f5 CL	146	`DECODE_ALU_SWP: if(!inbubble) begin
	147	outstall = rw_wait;
	148	next_outbubble = rw_wait;
	149	busaddr = {op0[31:2], 2'b0};
2bcc55d5	150	data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5 CL	151	case(swp_state)
	152	2'b01: begin
	153	rd_req = 1'b1;
	154	outstall = 1'b1;
	155	if(!rw_wait) begin
	156	next_swp_state = 2'b10;
	157	next_swp_oldval = rd_data;
9a0d0e43	158	end
fb529aac	159	$display("SWP: read stage");
9a0d0e43	160	end
5989b2f5 CL	161	2'b10: begin
5989b2f5 CL	162	wr_req = 1'b1;
2bcc55d5	163	wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5 CL	164	next_write_reg = 1'b1;
5989b2f5 CL	165	next_write_num = insn[15:12];
2bcc55d5	166	next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5 CL	167	if(!rw_wait)
5989b2f5 CL	168	next_swp_state = 2'b01;
fb529aac	169	$display("SWP: write stage");
5989b2f5 CL	170	end
	171	default: begin end
	172	endcase
9a0d0e43	173	end
fb529aac	174	`DECODE_ALU_MULT: begin end
666ceb03 CL	175	`DECODE_ALU_HDATA_REG,
	176	`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
	177	next_outbubble = rw_wait;
	178	outstall = rw_wait;
	179	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	180	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	181	busaddr = raddr;
	182	/* rotate to correct position */
	183	case(insn[6:5])
	184	2'b00: begin end /* swp */
	185	2'b01: begin /* unsigned half */
	186	wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5	187	data_size = 3'b010;
666ceb03 CL	188	lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
	189	end
	190	2'b10: begin /* signed byte */
	191	wr_data = {4{op2[7:0]}};
2bcc55d5	192	data_size = 3'b001;
666ceb03 CL	193	lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
	194	lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
	195	lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
	196	end
	197	2'b11: begin /* signed half */
	198	wr_data = {2{op2[15:0]}};
2bcc55d5	199	data_size = 3'b010;
666ceb03 CL	200	lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
	201	end
	202	endcase
	203
	204	case(lsrh_state)
4d7253f1	205	3'b001: begin
666ceb03 CL	206	rd_req = insn[20];
	207	wr_req = ~insn[20];
	208	next_write_num = insn[15:12];
	209	next_write_data = lsrh_rddata;
	210	if(insn[20]) begin
	211	next_write_reg = 1'b1;
	212	end
d64d6ef9	213	if(insn[21] \| !insn[24]) begin
666ceb03 CL	214	outstall = 1'b1;
666ceb03 CL	215	if(!rw_wait)
4d7253f1	216	next_lsrh_state = 3'b010;
666ceb03	217	end
fb529aac	218	$display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
666ceb03	219	end
4d7253f1 JW	220	3'b010: begin
4d7253f1 JW	221	next_outbubble = 1'b0;
666ceb03 CL	222	next_write_reg = 1'b1;
	223	next_write_num = insn[19:16];
	224	next_write_data = addr;
4d7253f1 JW	225	next_lsrh_state = 3'b100;
	226	end
	227	3'b100: begin
	228	outstall = 0;
	229	next_lsrh_state = 3'b001;
666ceb03 CL	230	end
	231	default: begin end
	232	endcase
d64d6ef9 JW	233
	234	if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
	235	outstall = 1'b0;
	236	next_lsrh_state = 3'b001;
	237	end
666ceb03	238	end
b3bb2fb8	239	`DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 CL	240	`DECODE_LDRSTR: if(!inbubble) begin
	241	next_outbubble = rw_wait;
	242	outstall = rw_wait;
	243	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be	244	raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03 CL	245	busaddr = raddr;
666ceb03 CL	246	/* rotate to correct position */
5989b2f5 CL	247	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	248	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	249	/* select byte or word */
	250	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
666ceb03	251	wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
2bcc55d5	252	data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5	253	case(lsr_state)
4d7253f1	254	3'b001: begin
fb529aac JW	255	rd_req = insn[20] /* L */;
	256	wr_req = ~insn[20] /* L */;
	257	next_write_reg = insn[20] /* L */;
666ceb03	258	next_write_num = insn[15:12];
fb529aac	259	if(insn[20] /* L */) begin
5989b2f5	260	next_write_data = align_rddata;
a02ca509	261	end
d64d6ef9	262	if(insn[21] /* W / \| !insn[24] / P */) begin
5989b2f5 CL	263	outstall = 1'b1;
5989b2f5 CL	264	if(!rw_wait)
4d7253f1	265	next_lsr_state = 3'b010;
a02ca509	266	end
d73619a2	267	$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8	268	end
4d7253f1 JW	269	3'b010: begin
	270	outstall = 1;
	271	next_outbubble = 0;
5989b2f5 CL	272	next_write_reg = 1'b1;
	273	next_write_num = insn[19:16];
	274	next_write_data = addr;
4d7253f1 JW	275	next_lsr_state = 3'b100;
	276	end
	277	3'b100: begin
	278	outstall = 0;
	279	next_lsr_state = 3'b001;
5989b2f5 CL	280	end
	281	default: begin end
	282	endcase
d64d6ef9 JW	283
	284	if ((lsr_state == 3'b001) && flush) begin /* Reject it. */
	285	outstall = 1'b0;
	286	next_lsr_state = 3'b001;
	287	end
b3bb2fb8	288	end
5989b2f5 CL	289	/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
5989b2f5 CL	290	`DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 CL	291	outstall = rw_wait;
9a0d0e43 CL	292	next_outbubble = rw_wait;
2bcc55d5	293	data_size = 3'b100;
9a0d0e43	294	case(lsm_state)
4d7253f1	295	4'b0001: begin
b114e03f CL	296	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
b114e03f CL	297	/** verilator can suck my dick */
b957d34d JW	298	$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
	299	next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	300	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f	301	offset = 6'b0;
d64d6ef9 JW	302	outstall = 1'b1;
d64d6ef9 JW	303	next_lsm_state = 4'b0010;
e08b748a	304	end
4d7253f1	305	4'b0010: begin
9a0d0e43 CL	306	rd_req = insn[20];
9a0d0e43 CL	307	wr_req = ~insn[20];
9f082c0b CL	308	casez(regs)
9f082c0b CL	309	16'b???????????????1: begin
e08b748a	310	cur_reg = 4'h0;
b114e03f	311	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	312	end
9f082c0b CL	313	16'b??????????????10: begin
e08b748a	314	cur_reg = 4'h1;
b114e03f	315	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	316	end
9f082c0b CL	317	16'b?????????????100: begin
e08b748a	318	cur_reg = 4'h2;
b114e03f	319	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	320	end
9f082c0b CL	321	16'b????????????1000: begin
e08b748a	322	cur_reg = 4'h3;
b114e03f	323	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	324	end
9f082c0b CL	325	16'b???????????10000: begin
e08b748a	326	cur_reg = 4'h4;
b114e03f	327	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	328	end
9f082c0b CL	329	16'b??????????100000: begin
e08b748a	330	cur_reg = 4'h5;
b114e03f	331	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	332	end
9f082c0b CL	333	16'b?????????1000000: begin
e08b748a	334	cur_reg = 4'h6;
b114e03f	335	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	336	end
9f082c0b CL	337	16'b????????10000000: begin
e08b748a	338	cur_reg = 4'h7;
b114e03f	339	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	340	end
9f082c0b CL	341	16'b???????100000000: begin
e08b748a	342	cur_reg = 4'h8;
b114e03f	343	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	344	end
9f082c0b CL	345	16'b??????1000000000: begin
e08b748a	346	cur_reg = 4'h9;
b114e03f	347	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	348	end
9f082c0b CL	349	16'b?????10000000000: begin
e08b748a	350	cur_reg = 4'hA;
b114e03f	351	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	352	end
9f082c0b CL	353	16'b????100000000000: begin
e08b748a	354	cur_reg = 4'hB;
b114e03f	355	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	356	end
9f082c0b CL	357	16'b???1000000000000: begin
e08b748a	358	cur_reg = 4'hC;
b114e03f	359	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	360	end
9f082c0b CL	361	16'b??10000000000000: begin
e08b748a	362	cur_reg = 4'hD;
b114e03f	363	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	364	end
9f082c0b CL	365	16'b?100000000000000: begin
e08b748a	366	cur_reg = 4'hE;
b114e03f	367	next_regs = {regs[15], 15'b0};
9f082c0b CL	368	end
9f082c0b CL	369	16'b1000000000000000: begin
e08b748a	370	cur_reg = 4'hF;
9f082c0b CL	371	next_regs = 16'b0;
	372	end
	373	default: begin
e08b748a CL	374	cur_reg = 4'hx;
e08b748a CL	375	next_regs = 16'b0;
9f082c0b CL	376	end
9f082c0b CL	377	endcase
b957d34d	378	cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13 CL	379	if(cur_reg == 4'hF && insn[22]) begin
efd1aa13 CL	380	next_outcpsr = spsr;
fdecc897	381	next_outcpsrup = 1;
efd1aa13	382	end
b114e03f	383
95704fd3	384	offset = prev_offset + 6'h4;
d73619a2 JW	385	offset_sel = insn[24] ? offset : prev_offset;
	386	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	387	if(insn[20]) begin
	388	next_write_reg = !rw_wait;
	389	next_write_num = cur_reg;
	390	next_write_data = rd_data;
	391	end
	392	if (rw_wait) begin
	393	next_regs = regs;
	394	cur_reg = prev_reg; /* whoops, do this one again */
b114e03f CL	395	end
	396
	397	st_read = cur_reg;
b957d34d	398	wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03	399	busaddr = raddr;
b957d34d	400
d73619a2	401	$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43 CL	402
	403	outstall = 1'b1;
	404
	405	if(next_regs == 16'b0) begin
4d7253f1	406	next_lsm_state = 4'b0100;
9a0d0e43 CL	407	end
9a0d0e43 CL	408	end
4d7253f1 JW	409	4'b0100: begin
	410	outstall = 1;
	411	next_outbubble = 0;
b957d34d	412	next_write_reg = insn[21] /* writeback */;
9a0d0e43 CL	413	next_write_num = insn[19:16];
9a0d0e43 CL	414	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
4d7253f1	415	next_lsm_state = 4'b1000;
d73619a2	416	$display("LDMSTM: Stage 3: Writing back");
b783a475	417	end
4d7253f1 JW	418	4'b1000: begin
	419	outstall = 0;
	420	next_lsm_state = 4'b0001;
	421	end
d73619a2	422	default: $stop;
9a0d0e43	423	endcase
d64d6ef9 JW	424	if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
	425	outstall = 1'b0;
	426	next_lsm_state = 4'b0001;
	427	end
d73619a2	428	$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8	429	end
5989b2f5	430	`DECODE_LDCSTC: if(!inbubble) begin
43e4332c JW	431	$display("WARNING: Unimplemented LDCSTC");
43e4332c JW	432	end
5989b2f5	433	`DECODE_CDP: if(!inbubble) begin
43e4332c JW	434	cp_req = 1;
	435	if (cp_busy) begin
	436	outstall = 1;
	437	next_outbubble = 1;
	438	end
	439	if (!cp_ack) begin
	440	/* XXX undefined instruction trap */
	441	$display("WARNING: Possible CDP undefined instruction");
	442	end
	443	end
5989b2f5	444	`DECODE_MRCMCR: if(!inbubble) begin
43e4332c JW	445	cp_req = 1;
	446	cp_rnw = insn[20] /* L */;
	447	if (insn[20] == 0 /* store to coprocessor */)
	448	cp_write = op0;
	449	else begin
d1d0eb8e JW	450	if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
	451	next_write_reg = 1'b1;
	452	next_write_num = insn[15:12];
	453	next_write_data = cp_read;
fdecc897	454	end else begin
d1d0eb8e	455	next_outcpsr = {cp_read[31:28], cpsr[27:0]};
fdecc897 JW	456	next_outcpsrup = 1;
fdecc897 JW	457	end
43e4332c JW	458	end
	459	if (cp_busy) begin
	460	outstall = 1;
	461	next_outbubble = 1;
	462	end
	463	if (!cp_ack) begin
838e283e	464	$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c	465	end
838e283e	466	$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c	467	end
b3bb2fb8 CL	468	default: begin end
b3bb2fb8 CL	469	endcase
d73619a2 JW	470
	471	if ((flush \|\| delayedflush) && !outstall)
	472	next_outbubble = 1'b1;
b3bb2fb8	473	end
b3bb2fb8	474	endmodule