Issue.v: lol@me; stall was not getting propagated
[firearm.git] / Fetch.v
CommitLineData
bd073175
JW
1module Fetch(
2 input clk,
3 input Nrst,
4
5 output wire [31:0] rd_addr,
6 output wire rd_req,
7 input rd_wait,
8 input [31:0] rd_data,
9
10 input stall,
11 input jmp,
45fa96c0 12 input [31:0] jmppc,
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JW
13 output reg bubble = 1,
14 output reg [31:0] insn = 0,
15 output reg [31:0] pc = 0);
bd073175
JW
16
17 reg [31:0] prevpc;
90ff449a 18 reg [31:0] nextpc;
bd073175 19 initial
45fa96c0 20 prevpc = 32'hFFFFFFFC; /* ugh... the first pc we request will be this +4 */
bd073175 21 always @(negedge Nrst)
45fa96c0 22 prevpc <= 32'hFFFFFFFC;
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23
24 always @(*)
bd073175 25 if (!Nrst)
90ff449a 26 nextpc = 32'hFFFFFFFC;
bd073175 27 else if (stall) /* don't change any internal state */
90ff449a 28 nextpc = prevpc;
bd073175 29 else if (jmp)
90ff449a 30 nextpc = jmppc;
bd073175 31 else
90ff449a 32 nextpc = prevpc + 32'h4;
bd073175 33
171401a8 34 assign rd_addr = nextpc;
bd073175 35 assign rd_req = !stall;
bd073175
JW
36
37 always @(posedge clk)
90ff449a 38 begin
45fa96c0 39 if (!rd_wait || !Nrst)
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40 prevpc <= nextpc;
41 if (!stall)
42 begin
43 bubble <= rd_wait;
44 insn <= rd_data;
45 pc <= nextpc;
46 end
47 end
bd073175 48endmodule
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