ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
[firearm.git] / Execute.v
CommitLineData
5b3daee2
JW
1module Execute(
2 input clk,
3 input Nrst, /* XXX not used yet */
4
5 input stall,
6 input flush,
7
8 input inbubble,
9 input [31:0] pc,
10 input [31:0] insn,
11 input [31:0] cpsr,
cb0428b6 12 input [31:0] spsr,
3f5cefe1
JW
13 input [31:0] op0,
14 input [31:0] op1,
15 input [31:0] op2,
16 input carry,
5b3daee2
JW
17
18 output reg outstall = 0,
bc572c5f 19 output reg outbubble = 1,
6e3dfd79 20 output reg [31:0] outcpsr = 0,
cb0428b6 21 output reg [31:0] outspsr = 0,
fdecc897 22 output reg outcpsrup = 0,
bc572c5f
JW
23 output reg write_reg = 1'bx,
24 output reg [3:0] write_num = 4'bxxxx,
314dac21 25 output reg [31:0] write_data = 32'hxxxxxxxx,
149bcd1a 26 output reg [31:0] jmppc,
2393422a
JW
27 output reg jmp,
28 output reg [31:0] outpc,
c65110a8
JW
29 output reg [31:0] outinsn,
30 output reg [31:0] outop0, outop1, outop2
5b3daee2 31 );
5b3daee2 32
bc572c5f
JW
33 reg mult_start;
34 reg [31:0] mult_acc0, mult_in0, mult_in1;
35 wire mult_done;
36 wire [31:0] mult_result;
37
2b091cd4
JW
38 reg [31:0] alu_in0, alu_in1;
39 reg [3:0] alu_op;
40 reg alu_setflags;
6e3dfd79 41 wire [31:0] alu_result, alu_outcpsr;
732b7730
JW
42 wire alu_setres;
43
44 reg next_outbubble;
cb0428b6 45 reg [31:0] next_outcpsr, next_outspsr;
fdecc897 46 reg next_outcpsrup;
732b7730
JW
47 reg next_write_reg;
48 reg [3:0] next_write_num;
149bcd1a 49
732b7730 50 reg [31:0] next_write_data;
149bcd1a 51
bc572c5f
JW
52 Multiplier multiplier(
53 .clk(clk), .Nrst(Nrst),
54 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
55 .in1(mult_in1), .done(mult_done), .result(mult_result));
6e3dfd79
JW
56
57 ALU alu(
58 .clk(clk), .Nrst(Nrst),
59 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
60 .setflags(alu_setflags), .shifter_carry(carry),
732b7730 61 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
b770ec9a 62
732b7730
JW
63 always @(posedge clk)
64 begin
65 if (!stall)
66 begin
67 outbubble <= next_outbubble;
68 outcpsr <= next_outcpsr;
cb0428b6 69 outspsr <= next_outspsr;
fdecc897 70 outcpsrup <= next_outcpsrup;
732b7730
JW
71 write_reg <= next_write_reg;
72 write_num <= next_write_num;
73 write_data <= next_write_data;
2393422a
JW
74 outpc <= pc;
75 outinsn <= insn;
c65110a8
JW
76 outop0 <= op0;
77 outop1 <= op1;
78 outop2 <= op2;
732b7730
JW
79 end
80 end
b770ec9a
JW
81
82 reg delayedflush = 0;
83 always @(posedge clk)
84 if (flush && outstall /* halp! I can't do it now, maybe later? */)
85 delayedflush <= 1;
86 else if (!outstall /* anything has been handled this time around */)
87 delayedflush <= 0;
2b091cd4 88
af096d96
JW
89 reg prevstall = 0;
90 always @(posedge clk)
91 prevstall <= outstall;
3ccca009 92
2b091cd4 93 always @(*)
732b7730
JW
94 begin
95 outstall = stall;
3ccca009
JW
96
97 casez (insn)
98 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
99 outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
100 endcase
101 end
102
103 /* ALU inputs */
104 always @(*)
105 begin
106 alu_in0 = op0;
107 alu_in1 = op1;
108 alu_op = insn[24:21];
109 alu_setflags = insn[20] /* S */;
110 end
111
112 /* Register outputs */
113 always @(*)
114 begin
732b7730 115 next_outcpsr = cpsr;
cb0428b6 116 next_outspsr = spsr;
fdecc897 117 next_outcpsrup = 0;
732b7730
JW
118 next_write_reg = 0;
119 next_write_num = 4'hx;
120 next_write_data = 32'hxxxxxxxx;
3ccca009
JW
121
122 casez(insn)
af096d96
JW
123 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
124 begin
af096d96 125 next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
fdecc897 126 next_outcpsrup = insn[20] /* S */;
af096d96
JW
127 next_write_reg = 1;
128 next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
129 next_write_data = mult_result;
130 end
cb0428b6
JW
131 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
132 begin
133 next_write_reg = 1;
134 next_write_num = insn[15:12];
135 if (insn[22] /* Ps */)
136 next_write_data = spsr;
137 else
138 next_write_data = cpsr;
139 end
2b091cd4 140 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
cb0428b6 141 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
fdecc897 142 begin
cb0428b6
JW
143 if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0)) /* flags only */
144 begin
145 if (insn[22] /* Ps */)
146 next_outspsr = {op0[31:29], spsr[28:0]};
147 else
148 next_outcpsr = {op0[31:29], cpsr[28:0]};
149 end else begin
150 if (insn[22] /* Ps */)
151 next_outspsr = op0;
152 else
153 next_outcpsr = op0;
154 end
fdecc897
JW
155 next_outcpsrup = 1;
156 end
2b091cd4
JW
157 `DECODE_ALU_SWP, /* Atomic swap */
158 `DECODE_ALU_BX, /* Branch */
159 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
732b7730
JW
160 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
161 begin end
162 `DECODE_ALU: /* ALU */
163 begin
732b7730
JW
164 if (alu_setres) begin
165 next_write_reg = 1;
166 next_write_num = insn[15:12] /* Rd */;
167 next_write_data = alu_result;
168 end
169
3ccca009
JW
170 if (insn[20] /* S */) begin
171 next_outcpsrup = 1;
172 next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
173 end
174 end
175 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
176 `DECODE_LDRSTR, /* Single data transfer */
177 `DECODE_LDMSTM: /* Block data transfer */
178 begin end
179 `DECODE_BRANCH: /* Branch */
180 begin
181 if(insn[24] /* L */) begin
182 next_write_reg = 1;
183 next_write_num = 4'hE; /* link register */
184 next_write_data = pc + 32'h4;
185 end
732b7730 186 end
3ccca009
JW
187 endcase
188 end
189
190 /* Multiplier inputs */
191 always @(*)
192 begin
193 mult_start = 0;
194 mult_acc0 = 32'hxxxxxxxx;
195 mult_in0 = 32'hxxxxxxxx;
196 mult_in1 = 32'hxxxxxxxx;
197
198 casez(insn)
199 `DECODE_ALU_MULT:
200 begin
201 if (!prevstall /* i.e., this is a new one */ && !inbubble /* i.e., this is a real one */)
202 begin
203 mult_start = 1;
204 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
205 mult_in0 = op1 /* Rm */;
206 mult_in1 = op2 /* Rs */;
207 $display("New MUL instruction");
208 end
209 end
210 endcase
211 end
212
213 /* Miscellaneous cleanup. */
214 always @(*)
215 begin
216 next_outbubble = inbubble | flush | delayedflush;
217
218 jmp = 1'b0;
219 jmppc = 32'h00000000;
220
221 casez (insn)
222 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
223 next_outbubble = next_outbubble | !mult_done | !prevstall;
224 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
225 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
226 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
227 `DECODE_ALU_SWP, /* Atomic swap */
228 `DECODE_ALU_BX, /* Branch */
229 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
230 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - immediate offset */
231 `DECODE_ALU, /* ALU */
2b091cd4
JW
232 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
233 `DECODE_LDRSTR, /* Single data transfer */
314dac21
CL
234 `DECODE_LDMSTM: /* Block data transfer */
235 begin end
236 `DECODE_BRANCH:
237 begin
04281f32 238 if(!inbubble && !flush && !delayedflush && !outstall /* Let someone else take precedence. */) begin
f8bf38ca 239 jmppc = pc + op0 + 32'h8;
f8bf38ca 240 jmp = 1'b1;
314dac21
CL
241 end
242 end /* Branch */
2b091cd4
JW
243 `DECODE_LDCSTC, /* Coprocessor data transfer */
244 `DECODE_CDP, /* Coprocessor data op */
245 `DECODE_MRCMCR, /* Coprocessor register transfer */
246 `DECODE_SWI: /* SWI */
247 begin end
248 default: /* X everything else out */
249 begin end
250 endcase
732b7730 251 end
5b3daee2 252endmodule
07fbfa80
JW
253
254module Multiplier(
255 input clk,
256 input Nrst, /* XXX not used yet */
257
258 input start,
259 input [31:0] acc0,
260 input [31:0] in0,
261 input [31:0] in1,
262
263 output reg done = 0,
264 output reg [31:0] result);
265
266 reg [31:0] bitfield;
267 reg [31:0] multiplicand;
268 reg [31:0] acc;
269
270 always @(posedge clk)
271 begin
272 if (start) begin
273 bitfield <= in0;
274 multiplicand <= in1;
275 acc <= acc0;
276 done <= 0;
277 end else begin
278 bitfield <= {2'b00, bitfield[31:2]};
279 multiplicand <= {multiplicand[29:0], 2'b00};
280 acc <= acc +
281 (bitfield[0] ? multiplicand : 0) +
282 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
283 if (bitfield == 0) begin
284 result <= acc;
285 done <= 1;
286 end
287 end
288 end
289endmodule
879a3986 290
879a3986
CL
291module ALU(
292 input clk,
293 input Nrst, /* XXX not used yet */
294
295 input [31:0] in0,
296 input [31:0] in1,
297 input [31:0] cpsr,
298 input [3:0] op,
299 input setflags,
300 input shifter_carry,
301
302 output reg [31:0] result,
303 output reg [31:0] cpsr_out,
732b7730 304 output reg setres
879a3986 305);
7947b9c7
JW
306 reg [31:0] res;
307 reg flag_n, flag_z, flag_c, flag_v;
879a3986 308 wire [32:0] sum, diff, rdiff;
793482e9 309 wire sum_v, diff_v, rdiff_v;
879a3986
CL
310
311 assign sum = {1'b0, in0} + {1'b0, in1};
312 assign diff = {1'b0, in0} - {1'b0, in1};
a4c270c7 313 assign rdiff = {1'b0, in1} - {1'b0, in0};
793482e9
CL
314 assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
315 assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
316 assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
879a3986 317
879a3986
CL
318 always @(*) begin
319 res = 32'hxxxxxxxx;
320 setres = 1'bx;
321 flag_c = cpsr[`CPSR_C];
322 flag_v = cpsr[`CPSR_V];
323 case(op)
324 `ALU_AND: begin
732b7730 325 result = in0 & in1;
879a3986
CL
326 flag_c = shifter_carry;
327 setres = 1'b1;
328 end
329 `ALU_EOR: begin
732b7730 330 result = in0 ^ in1;
879a3986
CL
331 flag_c = shifter_carry;
332 setres = 1'b1;
333 end
334 `ALU_SUB: begin
732b7730 335 {flag_c, result} = diff;
1bc060d9 336 flag_c = !flag_c;
793482e9 337 flag_v = diff_v;
879a3986
CL
338 setres = 1'b1;
339 end
340 `ALU_RSB: begin
732b7730 341 {flag_c, result} = rdiff;
1bc060d9 342 flag_c = !flag_c;
793482e9 343 flag_v = rdiff_v;
879a3986
CL
344 setres = 1'b1;
345 end
346 `ALU_ADD: begin
732b7730 347 {flag_c, result} = sum;
793482e9 348 flag_v = sum_v;
879a3986
CL
349 setres = 1'b1;
350 end
351 `ALU_ADC: begin
732b7730 352 {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
793482e9 353 flag_v = sum_v | (~sum[31] & result[31]);
879a3986
CL
354 setres = 1'b1;
355 end
356 `ALU_SBC: begin
732b7730 357 {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
1bc060d9 358 flag_c = !flag_c;
793482e9 359 flag_v = diff_v | (diff[31] & ~result[31]);
879a3986
CL
360 setres = 1'b1;
361 end
362 `ALU_RSC: begin
732b7730 363 {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
1bc060d9 364 flag_c = !flag_c;
793482e9 365 flag_v = rdiff_v | (rdiff[31] & ~result[31]);
879a3986
CL
366 setres = 1'b1;
367 end
368 `ALU_TST: begin
732b7730 369 result = in0 & in1;
879a3986
CL
370 flag_c = shifter_carry;
371 setres = 1'b0;
372 end
373 `ALU_TEQ: begin
732b7730 374 result = in0 ^ in1;
879a3986
CL
375 flag_c = shifter_carry;
376 setres = 1'b0;
377 end
378 `ALU_CMP: begin
732b7730 379 {flag_c, result} = diff;
1bc060d9 380 flag_c = !flag_c;
793482e9 381 flag_v = diff_v;
879a3986
CL
382 setres = 1'b0;
383 end
384 `ALU_CMN: begin
732b7730 385 {flag_c, result} = sum;
793482e9 386 flag_v = sum_v;
879a3986
CL
387 setres = 1'b0;
388 end
389 `ALU_ORR: begin
732b7730 390 result = in0 | in1;
879a3986
CL
391 flag_c = shifter_carry;
392 setres = 1'b1;
393 end
394 `ALU_MOV: begin
732b7730 395 result = in1;
879a3986
CL
396 flag_c = shifter_carry;
397 setres = 1'b1;
398 end
399 `ALU_BIC: begin
732b7730 400 result = in0 & (~in1);
879a3986
CL
401 flag_c = shifter_carry;
402 setres = 1'b1;
403 end
404 `ALU_MVN: begin
732b7730 405 result = ~in1;
879a3986
CL
406 flag_c = shifter_carry;
407 setres = 1'b1;
408 end
409 endcase
732b7730
JW
410
411 flag_z = (result == 0);
412 flag_n = result[31];
413
414 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986 415 end
879a3986 416endmodule
This page took 0.07568 seconds and 4 git commands to generate.