[firearm.git] / system.v

`define BUS_ICACHE 1
`define BUS_DCACHE 0

module System(input clk);
	wire [7:0] bus_req;
	wire [7:0] bus_ack;
	wire [31:0] bus_addr;
	wire [31:0] bus_rdata;
	wire [31:0] bus_wdata;
	wire bus_rd, bus_wr;
	wire bus_ready;

	wire bus_req_icache;
	wire bus_req_dcache;
	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
	
	wire [31:0] bus_addr_icache;
	wire [31:0] bus_wdata_icache;
	wire bus_rd_icache;
	wire bus_wr_icache;
	
	wire [31:0] bus_addr_dcache;
	wire [31:0] bus_wdata_dcache;
	wire bus_rd_dcache;
	wire bus_wr_dcache;
	
	wire [31:0] bus_rdata_blockram;
	wire bus_ready_blockram;
	
	assign bus_addr = bus_addr_icache | bus_addr_dcache;
	assign bus_rdata = bus_rdata_blockram;
	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
	assign bus_rd = bus_rd_icache | bus_rd_dcache;
	assign bus_wr = bus_wr_icache | bus_wr_dcache;
	assign bus_ready = bus_ready_blockram;

	wire [31:0] icache_rd_addr;
	wire icache_rd_req;
	wire icache_rd_wait;
	wire [31:0] icache_rd_data;
	
	wire [31:0] dcache_addr;
	wire dcache_rd_req, dcache_wr_req;
	wire dcache_rw_wait;
	wire [31:0] dcache_wr_data, dcache_rd_data;
	
	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
	wire decode_out_carry;
	
	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
	wire regfile_write;
	wire [3:0] regfile_write_reg;
	wire [31:0] regfile_write_data;
	
	wire execute_out_write_reg;
	wire [3:0] execute_out_write_num;
	wire [31:0] execute_out_write_data;
	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
	wire [31:0] execute_out_cpsr, execute_out_spsr;
	
	wire jmp_out_execute, jmp_out_writeback;
	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	wire jmp = jmp_out_execute | jmp_out_writeback;
	wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
	
	wire memory_out_write_reg;
	wire [3:0] memory_out_write_num;
	wire [31:0] memory_out_write_data;
	wire [31:0] memory_out_cpsr, memory_out_spsr;
	
	wire [31:0] writeback_out_cpsr, writeback_out_spsr;

	wire cp_ack_terminal;
	wire cp_busy_terminal;
	wire [31:0] cp_read_terminal;
	
	wire cp_req;
	wire [31:0] cp_insn;
	wire cp_ack = cp_ack_terminal;
	wire cp_busy = cp_busy_terminal;
	wire cp_rnw;
	wire [31:0] cp_read = cp_read_terminal;
	wire [31:0] cp_write;
	
	wire stall_cause_issue;
	wire stall_cause_execute;
	wire stall_cause_memory;
	wire bubble_out_fetch;
	wire bubble_out_issue;
	wire bubble_out_execute;
	wire bubble_out_memory;
	wire [31:0] insn_out_fetch;
	wire [31:0] insn_out_issue;
	wire [31:0] insn_out_execute;
	wire [31:0] insn_out_memory;
	wire [31:0] pc_out_fetch;
	wire [31:0] pc_out_issue;
	wire [31:0] pc_out_execute;
	wire [31:0] pc_out_memory;

	wire execute_out_backflush;
	wire writeback_out_backflush;

	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));

	ICache icache(
		.clk(clk),
		/* XXX reset? */
		.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
		.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
		.bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
		.bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
		.bus_wr(bus_wr_icache), .bus_ready(bus_ready));
	
	DCache dcache(
		.clk(clk),
		.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
		.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));

	BlockRAM blockram(
		.clk(clk),
		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
		.bus_ready(bus_ready_blockram));

	Fetch fetch(
		.clk(clk),
		.Nrst(1'b1 /* XXX */),
		.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
		.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
		.stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
		.bubble(bubble_out_fetch), .insn(insn_out_fetch),
		.pc(pc_out_fetch));
	
	Issue issue(
		.clk(clk),
		.Nrst(1'b1 /* XXX */),
		.stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
		.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
		.inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
		.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
		.outpc(pc_out_issue), .outinsn(insn_out_issue));
	
	RegFile regfile(
		.clk(clk),
		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
		.spsr(regfile_spsr),
		.write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
	
	Decode decode(
		.clk(clk),
		.stall(stall_cause_execute),
		.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
		.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
		.carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	
	Execute execute(
		.clk(clk), .Nrst(1'b0),
		.stall(stall_cause_memory), .flush(writeback_out_backflush),
		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
		.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
		.op2(decode_out_op2), .carry(decode_out_carry),
		.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
		.write_data(execute_out_write_data),
		.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
		.outpc(pc_out_execute), .outinsn(insn_out_execute),
		.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
		.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
	assign execute_out_backflush = jmp;
	
	assign cp_insn = insn_out_execute;
	Memory memory(
		.clk(clk), .Nrst(1'b0),
		/* stall? */ .flush(writeback_out_backflush),
		.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
		.st_read(regfile_read_3), .st_data(regfile_rdata_3),
		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
		.spsr(execute_out_spsr), .cpsr(execute_out_cpsr),
		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
		.outpc(pc_out_memory), .outinsn(insn_out_memory),
		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
		.out_write_data(memory_out_write_data),
		.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
		.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr) /* XXX data_size */);
	
	Terminal terminal(	
		.clk(clk),
		.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
		.cp_read(cp_read_terminal), .cp_write(cp_write));
	
	Writeback writeback(
		.clk(clk),
		.inbubble(bubble_out_memory),
		.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
		.cpsr(memory_out_cpsr), .spsr(memory_out_spsr),
		.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
		.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
		.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	assign writeback_out_backflush = jmp_out_writeback;

	reg [31:0] clockno = 0;
	always @(posedge clk)
	begin
		clockno <= clockno + 1;
		$display("------------------------------------------------------------------------------");
		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
		$display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
		$display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
	end
endmodule
Commit	Line	Data
e3a9107a JW	1	`define BUS_ICACHE 1
e3a9107a JW	2	`define BUS_DCACHE 0
ee406839	3
f61f8d6f	4	module System(input clk);
ee406839 JW	5	wire [7:0] bus_req;
	6	wire [7:0] bus_ack;
	7	wire [31:0] bus_addr;
a0bb35e7 JW	8	wire [31:0] bus_rdata;
a0bb35e7 JW	9	wire [31:0] bus_wdata;
ee406839 JW	10	wire bus_rd, bus_wr;
ee406839 JW	11	wire bus_ready;
45fa96c0	12
03f45381 JW	13	wire bus_req_icache;
03f45381 JW	14	wire bus_req_dcache;
e3a9107a	15	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
ee406839	16	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
03f45381	17	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
45fa96c0	18
ee406839 JW	19	wire [31:0] bus_addr_icache;
	20	wire [31:0] bus_wdata_icache;
	21	wire bus_rd_icache;
	22	wire bus_wr_icache;
	23
03f45381 JW	24	wire [31:0] bus_addr_dcache;
	25	wire [31:0] bus_wdata_dcache;
	26	wire bus_rd_dcache;
	27	wire bus_wr_dcache;
	28
a0bb35e7 JW	29	wire [31:0] bus_rdata_blockram;
	30	wire bus_ready_blockram;
	31
03f45381	32	assign bus_addr = bus_addr_icache \| bus_addr_dcache;
a0bb35e7	33	assign bus_rdata = bus_rdata_blockram;
03f45381 JW	34	assign bus_wdata = bus_wdata_icache \| bus_wdata_dcache;
	35	assign bus_rd = bus_rd_icache \| bus_rd_dcache;
	36	assign bus_wr = bus_wr_icache \| bus_wr_dcache;
a0bb35e7	37	assign bus_ready = bus_ready_blockram;
149bcd1a	38
5d9760a4 JW	39	wire [31:0] icache_rd_addr;
	40	wire icache_rd_req;
	41	wire icache_rd_wait;
	42	wire [31:0] icache_rd_data;
09e28f01	43
03f45381 JW	44	wire [31:0] dcache_addr;
	45	wire dcache_rd_req, dcache_wr_req;
	46	wire dcache_rw_wait;
	47	wire [31:0] dcache_wr_data, dcache_rd_data;
	48
ab7ee9fc	49	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
42c1e610	50	wire decode_out_carry;
c65110a8 JW	51
	52	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
	53	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
ab7ee9fc JW	54	wire regfile_write;
	55	wire [3:0] regfile_write_reg;
	56	wire [31:0] regfile_write_data;
c65110a8	57
bc572c5f JW	58	wire execute_out_write_reg;
	59	wire [3:0] execute_out_write_num;
	60	wire [31:0] execute_out_write_data;
c65110a8	61	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
1e66d5d1	62	wire [31:0] execute_out_cpsr, execute_out_spsr;
ab7ee9fc JW	63
	64	wire jmp_out_execute, jmp_out_writeback;
	65	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
	66	wire jmp = jmp_out_execute \| jmp_out_writeback;
	67	wire [31:0] jmppc = jmppc_out_execute \| jmppc_out_writeback;
5ca27949	68
c65110a8 JW	69	wire memory_out_write_reg;
	70	wire [3:0] memory_out_write_num;
	71	wire [31:0] memory_out_write_data;
ab7ee9fc JW	72	wire [31:0] memory_out_cpsr, memory_out_spsr;
	73
	74	wire [31:0] writeback_out_cpsr, writeback_out_spsr;
1d97a095 JW	75
	76	wire cp_ack_terminal;
	77	wire cp_busy_terminal;
	78	wire [31:0] cp_read_terminal;
c65110a8	79
43e4332c	80	wire cp_req;
1d97a095 JW	81	wire [31:0] cp_insn;
	82	wire cp_ack = cp_ack_terminal;
	83	wire cp_busy = cp_busy_terminal;
43e4332c	84	wire cp_rnw;
1d97a095	85	wire [31:0] cp_read = cp_read_terminal;
43e4332c JW	86	wire [31:0] cp_write;
43e4332c JW	87
c65110a8 JW	88	wire stall_cause_issue;
	89	wire stall_cause_execute;
	90	wire stall_cause_memory;
09e28f01 JW	91	wire bubble_out_fetch;
09e28f01 JW	92	wire bubble_out_issue;
2393422a	93	wire bubble_out_execute;
c65110a8	94	wire bubble_out_memory;
09e28f01 JW	95	wire [31:0] insn_out_fetch;
09e28f01 JW	96	wire [31:0] insn_out_issue;
2393422a	97	wire [31:0] insn_out_execute;
c65110a8	98	wire [31:0] insn_out_memory;
09e28f01 JW	99	wire [31:0] pc_out_fetch;
09e28f01 JW	100	wire [31:0] pc_out_issue;
2393422a	101	wire [31:0] pc_out_execute;
c65110a8	102	wire [31:0] pc_out_memory;
149bcd1a	103
7947b9c7	104	wire execute_out_backflush;
ab7ee9fc	105	wire writeback_out_backflush;
c2b9d4b7	106
ee406839	107	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
a0bb35e7 JW	108
	109	ICache icache(
	110	.clk(clk),
5d9760a4 JW	111	/* XXX reset? */
	112	.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
	113	.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
ee406839	114	.bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
a0bb35e7	115	.bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
ee406839 JW	116	.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
ee406839 JW	117	.bus_wr(bus_wr_icache), .bus_ready(bus_ready));
45fa96c0	118
03f45381 JW	119	DCache dcache(
	120	.clk(clk),
	121	.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
	122	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
	123	.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
	124	.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
	125	.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
	126	.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
	127
a0bb35e7 JW	128	BlockRAM blockram(
	129	.clk(clk),
	130	.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
	131	.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
	132	.bus_ready(bus_ready_blockram));
	133
5d9760a4 JW	134	Fetch fetch(
5d9760a4 JW	135	.clk(clk),
f61f8d6f	136	.Nrst(1'b1 /* XXX */),
5d9760a4 JW	137	.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
5d9760a4 JW	138	.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
149bcd1a	139	.stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
09e28f01 JW	140	.bubble(bubble_out_fetch), .insn(insn_out_fetch),
	141	.pc(pc_out_fetch));
	142
	143	Issue issue(
	144	.clk(clk),
f61f8d6f	145	.Nrst(1'b1 /* XXX */),
ab7ee9fc	146	.stall(stall_cause_execute), .flush(execute_out_backflush \| writeback_out_backflush),
09e28f01	147	.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
ab7ee9fc	148	.inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
09e28f01 JW	149	.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
09e28f01 JW	150	.outpc(pc_out_issue), .outinsn(insn_out_issue));
90ff449a	151
5ca27949 JW	152	RegFile regfile(
5ca27949 JW	153	.clk(clk),
8077f6bb JW	154	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
8077f6bb JW	155	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
ab7ee9fc JW	156	.spsr(regfile_spsr),
ab7ee9fc JW	157	.write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
5ca27949 JW	158
	159	Decode decode(
	160	.clk(clk),
e74c7936	161	.stall(stall_cause_execute),
ab7ee9fc	162	.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
5ca27949	163	.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
ab7ee9fc	164	.carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
5ca27949 JW	165	.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
	166	.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
	167
bc572c5f	168	Execute execute(
f61f8d6f	169	.clk(clk), .Nrst(1'b0),
ab7ee9fc	170	.stall(stall_cause_memory), .flush(writeback_out_backflush),
bc572c5f	171	.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
ab7ee9fc	172	.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
bc572c5f	173	.op2(decode_out_op2), .carry(decode_out_carry),
2393422a	174	.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
bc572c5f	175	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
149bcd1a	176	.write_data(execute_out_write_data),
ab7ee9fc	177	.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
c65110a8	178	.outpc(pc_out_execute), .outinsn(insn_out_execute),
1e66d5d1 JW	179	.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
1e66d5d1 JW	180	.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
7947b9c7	181	assign execute_out_backflush = jmp;
c65110a8	182
1d97a095	183	assign cp_insn = insn_out_execute;
c65110a8 JW	184	Memory memory(
c65110a8 JW	185	.clk(clk), .Nrst(1'b0),
ab7ee9fc	186	/* stall? */ .flush(writeback_out_backflush),
b455d481 JW	187	.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
b455d481 JW	188	.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
c65110a8 JW	189	.st_read(regfile_read_3), .st_data(regfile_rdata_3),
	190	.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
	191	.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
1e66d5d1	192	.spsr(execute_out_spsr), .cpsr(execute_out_cpsr),
c65110a8 JW	193	.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
	194	.outstall(stall_cause_memory), .outbubble(bubble_out_memory),
	195	.outpc(pc_out_memory), .outinsn(insn_out_memory),
	196	.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
43e4332c	197	.out_write_data(memory_out_write_data),
ab7ee9fc	198	.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
8077f6bb	199	.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr) /* XXX data_size */);
1d97a095 JW	200
	201	Terminal terminal(
	202	.clk(clk),
	203	.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
	204	.cp_read(cp_read_terminal), .cp_write(cp_write));
ab7ee9fc JW	205
	206	Writeback writeback(
	207	.clk(clk),
	208	.inbubble(bubble_out_memory),
	209	.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
	210	.cpsr(memory_out_cpsr), .spsr(memory_out_spsr),
	211	.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
	212	.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
	213	.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
	214	assign writeback_out_backflush = jmp_out_writeback;
149bcd1a	215
ff39dfc7	216	reg [31:0] clockno = 0;
90ff449a JW	217	always @(posedge clk)
90ff449a JW	218	begin
ff39dfc7 JW	219	clockno <= clockno + 1;
ff39dfc7 JW	220	$display("------------------------------------------------------------------------------");
5ca27949 JW	221	$display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
5ca27949 JW	222	$display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
db2351c4	223	$display("%3d: DECODE: op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
3550fbf2	224	$display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
c65110a8	225	$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
ab7ee9fc	226	$display("%3d: WRITEB: CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
90ff449a	227	end
ee406839	228	endmodule