Add support for CellularRAM on Nexys2.
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
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3module Decode(
4 input clk,
e74c7936 5 input stall,
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6 input [31:0] insn_1a,
7 input [31:0] pc_1a,
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JW
8 input [31:0] cpsr_1a,
9 input [31:0] spsr_1a,
10 output reg [31:0] op0_2a,
11 output reg [31:0] op1_2a,
12 output reg [31:0] op2_2a,
13 output reg carry_2a,
14 output reg [31:0] cpsr_2a,
15 output reg [31:0] spsr_2a,
bae77231 16
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17 output reg [3:0] rf__read_0_1a,
18 output reg [3:0] rf__read_1_1a,
19 output reg [3:0] rf__read_2_1a,
20 input [31:0] rf__rdata_0_1a,
21 input [31:0] rf__rdata_1_1a,
22 input [31:0] rf__rdata_2_1a
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23 );
24
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25 wire [31:0] regs0, regs1, regs2;
26 reg [31:0] rpc;
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27 reg [31:0] op0_1a, op1_1a, op2_1a;
28 reg carry_1a;
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29
30 /* shifter stuff */
31 wire [31:0] shift_oper;
32 wire [31:0] shift_res;
33 wire shift_cflag_out;
a0c8a75c 34 wire [31:0] rotate_res;
bae77231 35
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36 assign regs0 = (rf__read_0_1a == 4'b1111) ? rpc : rf__rdata_0_1a;
37 assign regs1 = (rf__read_1_1a == 4'b1111) ? rpc : rf__rdata_1_1a;
38 assign regs2 = rf__rdata_2_1a; /* use regs2 for things that cannot be r15 */
bae77231 39
a7297aa5 40 IREALLYHATEARMSHIFT shift(.insn(insn_1a),
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41 .operand(regs1),
42 .reg_amt(regs2),
8c1ba494 43 .cflag_in(cpsr_1a[`CPSR_C]),
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44 .res(shift_res),
45 .cflag_out(shift_cflag_out));
e2c5d224 46
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47 SuckLessRotator whirr(.oper({24'b0, insn_1a[7:0]}),
48 .amt(insn_1a[11:8]),
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49 .res(rotate_res));
50
be64a9df 51 always @(*)
a7297aa5 52 casez (insn_1a)
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53 `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
54// `DECODE_ALU_MUL_LONG, /* Multiply long */
55 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
56 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
57 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
58 `DECODE_ALU_SWP, /* Atomic swap */
59 `DECODE_ALU_BX, /* Branch and exchange */
60 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
61 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
62 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
63 `DECODE_LDRSTR, /* Single data transfer */
64 `DECODE_LDMSTM, /* Block data transfer */
65 `DECODE_BRANCH, /* Branch */
66 `DECODE_LDCSTC, /* Coprocessor data transfer */
67 `DECODE_CDP, /* Coprocessor data op */
2c523f8a 68 `DECODE_SWI: /* SWI */
a7297aa5 69 rpc = pc_1a + 8;
04d95cf5 70 `DECODE_MRCMCR: /* Coprocessor register transfer */
a7297aa5 71 rpc = pc_1a + 12;
2c523f8a 72 `DECODE_ALU: /* ALU */
a7297aa5 73 rpc = pc_1a + (insn_1a[25] ? 8 : (insn_1a[4] ? 12 : 8));
2c523f8a 74 default: /* X everything else out */
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75 rpc = 32'hxxxxxxxx;
76 endcase
96f7e6e1 77
326fd4c3 78 always @(*) begin
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79 rf__read_0_1a = 4'hx;
80 rf__read_1_1a = 4'hx;
81 rf__read_2_1a = 4'hx;
326fd4c3 82
a7297aa5 83 casez (insn_1a)
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84 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
85 begin
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86 rf__read_0_1a = insn_1a[15:12]; /* Rn */
87 rf__read_1_1a = insn_1a[3:0]; /* Rm */
88 rf__read_2_1a = insn_1a[11:8]; /* Rs */
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89 end
90 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
91 begin end
92 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
a7297aa5 93 rf__read_0_1a = insn_1a[3:0]; /* Rm */
74b05f6e 94 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
a7297aa5 95 rf__read_0_1a = insn_1a[3:0]; /* Rm */
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96 `DECODE_ALU_SWP: /* Atomic swap */
97 begin
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98 rf__read_0_1a = insn_1a[19:16]; /* Rn */
99 rf__read_1_1a = insn_1a[3:0]; /* Rm */
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100 end
101 `DECODE_ALU_BX: /* Branch and exchange */
a7297aa5 102 rf__read_0_1a = insn_1a[3:0]; /* Rn */
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103 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
104 begin
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105 rf__read_0_1a = insn_1a[19:16];
106 rf__read_1_1a = insn_1a[3:0];
107 rf__read_2_1a = insn_1a[15:12];
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108 end
109 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
110 begin
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111 rf__read_0_1a = insn_1a[19:16];
112 rf__read_1_1a = insn_1a[15:12];
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113 end
114 `DECODE_ALU: /* ALU */
115 begin
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116 rf__read_0_1a = insn_1a[19:16]; /* Rn */
117 rf__read_1_1a = insn_1a[3:0]; /* Rm */
118 rf__read_2_1a = insn_1a[11:8]; /* Rs for shift */
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119 end
120 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
121 begin end
122 `DECODE_LDRSTR: /* Single data transfer */
123 begin
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124 rf__read_0_1a = insn_1a[19:16]; /* Rn */
125 rf__read_1_1a = insn_1a[3:0]; /* Rm */
126 rf__read_2_1a = insn_1a[15:12];
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127 end
128 `DECODE_LDMSTM: /* Block data transfer */
a7297aa5 129 rf__read_0_1a = insn_1a[19:16];
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130 `DECODE_BRANCH: /* Branch */
131 begin end
132 `DECODE_LDCSTC: /* Coprocessor data transfer */
a7297aa5 133 rf__read_0_1a = insn_1a[19:16];
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134 `DECODE_CDP: /* Coprocessor data op */
135 begin end
136 `DECODE_MRCMCR: /* Coprocessor register transfer */
a7297aa5 137 rf__read_0_1a = insn_1a[15:12];
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138 `DECODE_SWI: /* SWI */
139 begin end
140 default:
141 $display("Undecoded instruction");
142 endcase
143 end
144
145 always @(*) begin
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146 op0_1a = 32'hxxxxxxxx;
147 op1_1a = 32'hxxxxxxxx;
148 op2_1a = 32'hxxxxxxxx;
149 carry_1a = 1'bx;
96f7e6e1 150
a7297aa5 151 casez (insn_1a)
2c523f8a 152 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3 153 begin
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154 op0_1a = regs0;
155 op1_1a = regs1;
156 op2_1a = regs2;
326fd4c3 157 end
2c523f8a 158 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610 159 begin end
96f7e6e1 160 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
8c1ba494 161 op0_1a = regs0;
2c523f8a 162 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
a7297aa5 163 if(insn_1a[25]) begin /* the constant case */
8c1ba494 164 op0_1a = rotate_res;
96f7e6e1 165 end else begin
8c1ba494 166 op0_1a = regs0;
96f7e6e1 167 end
2c523f8a 168 `DECODE_ALU_SWP: /* Atomic swap */
326fd4c3 169 begin
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170 op0_1a = regs0;
171 op1_1a = regs1;
326fd4c3 172 end
2c523f8a 173 `DECODE_ALU_BX: /* Branch and exchange */
8c1ba494 174 op0_1a = regs0;
2c523f8a 175 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3 176 begin
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177 op0_1a = regs0;
178 op1_1a = regs1;
179 op2_1a = regs2;
326fd4c3 180 end
2c523f8a 181 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3 182 begin
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183 op0_1a = regs0;
184 op1_1a = {24'b0, insn_1a[11:8], insn_1a[3:0]};
185 op2_1a = regs1;
326fd4c3 186 end
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187 `DECODE_ALU: /* ALU */
188 begin
8c1ba494 189 op0_1a = regs0;
a7297aa5 190 if(insn_1a[25]) begin /* the constant case */
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191 carry_1a = cpsr_1a[`CPSR_C];
192 op1_1a = rotate_res;
2c523f8a 193 end else begin
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194 carry_1a = shift_cflag_out;
195 op1_1a = shift_res;
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196 end
197 end
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198 `DECODE_LDRSTR: /* Single data transfer */
199 begin
8c1ba494 200 op0_1a = regs0;
a7297aa5 201 if(!insn_1a[25] /* immediate */) begin
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202 op1_1a = {20'b0, insn_1a[11:0]};
203 carry_1a = cpsr_1a[`CPSR_C];
bae77231 204 end else begin
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205 op1_1a = shift_res;
206 carry_1a = shift_cflag_out;
bae77231 207 end
8c1ba494 208 op2_1a = regs2;
bae77231 209 end
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210 `DECODE_LDMSTM: /* Block data transfer */
211 begin
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212 op0_1a = regs0;
213 op1_1a = {16'b0, insn_1a[15:0]};
bae77231 214 end
96f7e6e1 215 `DECODE_BRANCH: /* Branch */
8c1ba494 216 op0_1a = {{6{insn_1a[23]}}, insn_1a[23:0], 2'b0};
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217 `DECODE_LDCSTC: /* Coprocessor data transfer */
218 begin
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219 op0_1a = regs0;
220 op1_1a = {24'b0, insn_1a[7:0]};
bae77231 221 end
96f7e6e1 222 `DECODE_CDP: /* Coprocessor data op */
74b05f6e 223 begin end
96f7e6e1 224 `DECODE_MRCMCR: /* Coprocessor register transfer */
8c1ba494 225 op0_1a = regs0;
96f7e6e1 226 `DECODE_SWI: /* SWI */
74b05f6e 227 begin end
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228 endcase
229 end
96f7e6e1 230
bae77231 231 always @ (posedge clk) begin
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232 if (!stall)
233 begin
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234 op0_2a <= op0_1a; /* Rn - always */
235 op1_2a <= op1_1a; /* 'operand 2' - Rm */
236 op2_2a <= op2_1a; /* thirdedge - Rs */
237 carry_2a <= carry_1a;
238 cpsr_2a <= cpsr_1a;
239 spsr_2a <= spsr_1a;
e74c7936 240 end
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241 end
242
243endmodule
244
e2c5d224 245module IREALLYHATEARMSHIFT(
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246 input [31:0] insn,
247 input [31:0] operand,
248 input [31:0] reg_amt,
249 input cflag_in,
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250 output reg [31:0] res,
251 output reg cflag_out
bae77231 252);
bae77231 253 wire [5:0] shift_amt;
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254 reg is_arith, is_rot;
255 wire rshift_cout;
256 wire [31:0] rshift_res;
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257
258 assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
259 : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231 260
96f7e6e1 261 SuckLessShifter barrel(.oper(operand),
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262 .carryin(cflag_in),
263 .amt(shift_amt),
264 .is_arith(is_arith),
265 .is_rot(is_rot),
266 .res(rshift_res),
267 .carryout(rshift_cout));
bae77231 268
821617bb 269 always @(*)
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CL
270 case (insn[6:5])
271 `SHIFT_LSL: begin
e5fb7d86 272 /* meaningless */
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CL
273 is_rot = 1'b0;
274 is_arith = 1'b0;
26049339 275 end
e2c5d224
CL
276 `SHIFT_LSR: begin
277 is_rot = 1'b0;
278 is_arith = 1'b0;
279 end
280 `SHIFT_ASR: begin
281 is_rot = 1'b0;
282 is_arith = 1'b1;
283 end
284 `SHIFT_ROR: begin
285 is_rot = 1'b1;
286 is_arith = 1'b0;
287 end
288 endcase
289
821617bb 290 always @(*)
26049339 291 case (insn[6:5]) /* shift type */
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CL
292 `SHIFT_LSL:
293 {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231 294 `SHIFT_LSR: begin
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295 res = rshift_res;
296 cflag_out = rshift_cout;
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CL
297 end
298 `SHIFT_ASR: begin
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299 res = rshift_res;
300 cflag_out = rshift_cout;
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301 end
302 `SHIFT_ROR: begin
e2c5d224 303 if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
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304 res = {cflag_in, operand[31:1]};
305 cflag_out = operand[0];
e5fb7d86 306 end else begin
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307 res = rshift_res;
308 cflag_out = rshift_cout;
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309 end
310 end
26049339 311 endcase
bae77231 312endmodule
e2c5d224
CL
313
314module SuckLessShifter(
315 input [31:0] oper,
316 input carryin,
317 input [5:0] amt,
318 input is_arith,
319 input is_rot,
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320 output wire [31:0] res,
321 output wire carryout
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CL
322);
323
324 wire [32:0] stage1, stage2, stage3, stage4, stage5;
325
e5fb7d86 326 wire pushbits = is_arith & oper[31];
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CL
327
328 /* do a barrel shift */
329 assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
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330 assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
331 assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
332 assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
333 assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
334 assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
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335
336endmodule
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337
338module SuckLessRotator(
339 input [31:0] oper,
340 input [3:0] amt,
f61f8d6f 341 output wire [31:0] res
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CL
342);
343
344 wire [31:0] stage1, stage2, stage3;
345 assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
346 assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
347 assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
348 assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
349
350endmodule
96f7e6e1 351
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