[firearm.git] / Memory.v

`include "ARM_Constants.v"

module Memory(
	input clk,
	input Nrst,

	/* bus interface */
	output reg [31:0] busaddr,
	output reg rd_req,
	output reg wr_req,
	input rw_wait,
	output reg [31:0] wr_data,
	input [31:0] rd_data,

	/* regfile interface */
	output reg [3:0] st_read,
	input [31:0] st_data,
	
	/* Coprocessor interface */
	output reg cp_req,
	input cp_ack,
	input cp_busy,
	output cp_rnw,	/* 1 = read from CP, 0 = write to CP */
	input [31:0] cp_read,
	output reg [31:0] cp_write,
	
	/* stage inputs */
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] spsr,
	input [31:0] cpsr,
	input write_reg,
	input [3:0] write_num,
	input [31:0] write_data,

	/* outputs */
	output reg outstall,
	output reg outbubble,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg out_write_reg = 1'b0,
	output reg [3:0] out_write_num = 4'bxxxx,
	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	output reg [31:0] out_cpsr = 32'hxxxxxxxx
	);

	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
	reg [3:0] next_regsel, cur_reg, prev_reg;
	reg next_writeback;
	reg [31:0] align_s1, align_s2, align_rddata;

	wire next_outbubble;	
	wire next_write_reg;
	wire [3:0] next_write_num;
	wire [31:0] next_write_data;

	reg [1:0] lsr_state = 2'b01, next_lsr_state;

	reg [15:0] regs, next_regs;
	reg [2:0] lsm_state = 3'b001, next_lsm_state;
	reg [5:0] offset, prev_offset, offset_sel;

	reg [31:0] swp_oldval, next_swp_oldval;
	reg [1:0] swp_state = 2'b01, next_swp_state;

	always @(posedge clk)
	begin
		outpc <= pc;
		outinsn <= insn;
		outbubble <= next_outbubble;
		out_write_reg <= next_write_reg;
		out_write_num <= next_write_num;
		out_write_data <= next_write_data;
		regs <= next_regs;
		prev_reg <= cur_reg;
		prev_offset <= offset;
		prev_raddr <= raddr;
		out_cpsr <= next_outcpsr;
		out_spsr <= spsr;
		swp_state <= next_swp_state;
	end

	always @(*)
	begin
		addr = 32'hxxxxxxxx;
		raddr = 32'hxxxxxxxx;
		rd_req = 1'b0;
		wr_req = 1'b0;
		wr_data = 32'hxxxxxxxx;
		busaddr = 32'hxxxxxxxx;
		outstall = 1'b0;
		next_write_reg = write_reg;
		next_write_num = write_num;
		next_write_data = write_data;
		next_outbubble = inbubble;
		outstall = 1'b0;
		next_regs = regs;
		cp_req = 1'b0;
		cp_rnw = 1'bx;
		cp_write = 32'hxxxxxxxx;
		offset = prev_offset;
		next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
		next_lsm_state = lsm_state;
		next_lsr_state = lsr_state;
		next_swp_oldval = swp_oldval;
		next_swp_state = swp_state;
		cur_reg = prev_reg;

		/* XXX shit not given about endianness */
		/* TODO ldrh/strh */
		casez(insn)
		`DECODE_ALU_SWP: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			busaddr = {op0[31:2], 2'b0};
			case(swp_state)
			2'b01: begin
				rd_req = 1'b1;
				outstall = 1'b1;
				if(!rw_wait) begin
					next_swp_state = 2'b10;
					next_swp_oldval = rd_data;
				end
			end
			2'b10: begin
				wr_req = 1'b1;
				wr_data = op1;
				next_write_reg = 1'b1;
				next_write_num = insn[15:12];
				next_write_data = swp_oldval;
				if(!rw_wait)
					next_swp_state = 2'b01;
			end
			default: begin end
			endcase
		end
		`DECODE_LDRSTR_UNDEFINED: begin end
		`DECODE_LDRSTR: if(!inbubble) begin
			next_outbubble = rw_wait;
			outstall = rw_wait;
			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
			raddr = insn[24] ? op0 : addr; /* pre/post increment */
			busaddr = {raddr[31:2], 2'b0};
				/* rotate to correct position */
			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
			/* select byte or word */
			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
			if(!insn[20]) begin
				wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
			end
			case(lsr_state)
			2'b01: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				if(insn[20]) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = align_rddata;
				end
					if(insn[21]) begin
					outstall = 1'b1;
					if(!rw_wait)
						next_lsr_state = 2'b10;
				end
			end
			2'b10: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = addr;
				next_lsr_state = 2'b10;
			end
			default: begin end
			endcase
		end
		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
		`DECODE_LDMSTM: if(!inbubble) begin
			outstall = rw_wait;
			next_outbubble = rw_wait;
			case(lsm_state)
			3'b001: begin
//				next_regs = insn[23] ? op1[15:0] : op1[0:15];
				/** verilator can suck my dick */
				next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
				                                    op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
				offset = 6'b0;
				outstall = 1'b1;
				next_lsm_state = 3'b010;
			end
			3'b010: begin
				rd_req = insn[20];
				wr_req = ~insn[20];
				casez(regs)
				16'b???????????????1: begin
					cur_reg = 4'h0;
					next_regs = {regs[15:1], 1'b0};
				end
				16'b??????????????10: begin
					cur_reg = 4'h1;
					next_regs = {regs[15:2], 2'b0};
				end
				16'b?????????????100: begin
					cur_reg = 4'h2;
					next_regs = {regs[15:3], 3'b0};
				end
				16'b????????????1000: begin
					cur_reg = 4'h3;
					next_regs = {regs[15:4], 4'b0};
				end
				16'b???????????10000: begin
					cur_reg = 4'h4;
					next_regs = {regs[15:5], 5'b0};
				end
				16'b??????????100000: begin
					cur_reg = 4'h5;
					next_regs = {regs[15:6], 6'b0};
				end
				16'b?????????1000000: begin
					cur_reg = 4'h6;
					next_regs = {regs[15:7], 7'b0};
				end
				16'b????????10000000: begin
					cur_reg = 4'h7;
					next_regs = {regs[15:8], 8'b0};
				end
				16'b???????100000000: begin
					cur_reg = 4'h8;
					next_regs = {regs[15:9], 9'b0};
				end
				16'b??????1000000000: begin
					cur_reg = 4'h9;
					next_regs = {regs[15:10], 10'b0};
				end
				16'b?????10000000000: begin
					cur_reg = 4'hA;
					next_regs = {regs[15:11], 11'b0};
				end
				16'b????100000000000: begin
					cur_reg = 4'hB;
					next_regs = {regs[15:12], 12'b0};
				end
				16'b???1000000000000: begin
					cur_reg = 4'hC;
					next_regs = {regs[15:13], 13'b0};
				end
				16'b??10000000000000: begin
					cur_reg = 4'hD;
					next_regs = {regs[15:14], 14'b0};
				end
				16'b?100000000000000: begin
					cur_reg = 4'hE;
					next_regs = {regs[15], 15'b0};
				end
				16'b1000000000000000: begin
					cur_reg = 4'hF;
					next_regs = 16'b0;
				end
				default: begin
					cur_reg = 4'hx;
					next_regs = 16'b0;
				end
				endcase
				cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
				if(cur_reg == 4'hF && insn[22]) begin
					next_outcpsr = spsr;
				end

				if(rw_wait) begin
					next_regs = regs;
					cur_reg = prev_reg;
					raddr = prev_raddr;
				end
				else begin
					offset = prev_offset + 6'h4;
					offset_sel = insn[24] ? offset : prev_offset;
					raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
					if(insn[20]) begin
						next_write_reg = 1'b1;
						next_write_num = cur_reg;
						next_write_data = rd_data;
					end
				end

				st_read = cur_reg;
				wr_data = st_data;
				busaddr = {raddr[31:2], 2'b0};

				outstall = 1'b1;

				if(next_regs == 16'b0) begin
					next_lsm_state = 3'b100;
				end
			end
			3'b100: begin
				next_write_reg = 1'b1;
				next_write_num = insn[19:16];
				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
				next_lsm_state = 3'b001;
			end
			default: begin end
			endcase
		end
		`DECODE_LDCSTC: if(!inbubble) begin
			$display("WARNING: Unimplemented LDCSTC");
		end
		`DECODE_CDP: if(!inbubble) begin
			cp_req = 1;
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				/* XXX undefined instruction trap */
				$display("WARNING: Possible CDP undefined instruction");
			end
		end
		`DECODE_MRCMCR: if(!inbubble) begin
			cp_req = 1;
			cp_rnw = insn[20] /* L */;
			if (insn[20] == 0 /* store to coprocessor */)
				cp_write = op0;
			else begin
				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
					next_write_reg = 1'b1;
					next_write_num = insn[15:12];
					next_write_data = cp_read;
				end else
					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
			end
			if (cp_busy) begin
				outstall = 1;
				next_outbubble = 1;
			end
			if (!cp_ack) begin
				$display("WARNING: Possible MRCMCR undefined instruction");
			end
		end
		default: begin end
		endcase
	end
endmodule
Commit	Line	Data
b3bb2fb8 CL	1	`include "ARM_Constants.v"
	2
	3	module Memory(
	4	input clk,
	5	input Nrst,
b3bb2fb8 CL	6
	7	/* bus interface */
	8	output reg [31:0] busaddr,
	9	output reg rd_req,
	10	output reg wr_req,
	11	input rw_wait,
	12	output reg [31:0] wr_data,
	13	input [31:0] rd_data,
	14
	15	/* regfile interface */
	16	output reg [3:0] st_read,
	17	input [31:0] st_data,
a02ca509	18
979f2bd7 JW	19	/* Coprocessor interface */
	20	output reg cp_req,
	21	input cp_ack,
	22	input cp_busy,
43e4332c JW	23	output cp_rnw, /* 1 = read from CP, 0 = write to CP */
	24	input [31:0] cp_read,
	25	output reg [31:0] cp_write,
979f2bd7	26
a02ca509 JW	27	/* stage inputs */
	28	input inbubble,
	29	input [31:0] pc,
	30	input [31:0] insn,
e68b2378 JW	31	input [31:0] op0,
e68b2378 JW	32	input [31:0] op1,
6d0f9d82	33	input [31:0] op2,
efd1aa13 CL	34	input [31:0] spsr,
efd1aa13 CL	35	input [31:0] cpsr,
a02ca509 JW	36	input write_reg,
	37	input [3:0] write_num,
	38	input [31:0] write_data,
b3bb2fb8	39
a02ca509 JW	40	/* outputs */
	41	output reg outstall,
	42	output reg outbubble,
b3bb2fb8	43	output reg [31:0] outpc,
a02ca509 JW	44	output reg [31:0] outinsn,
	45	output reg out_write_reg = 1'b0,
	46	output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 CL	47	output reg [31:0] out_write_data = 32'hxxxxxxxx,
	48	output reg [31:0] out_spsr = 32'hxxxxxxxx,
	49	output reg [31:0] out_cpsr = 32'hxxxxxxxx
a02ca509	50	);
b3bb2fb8	51
efd1aa13	52	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
e08b748a	53	reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43	54	reg next_writeback;
74d3729c	55	reg [31:0] align_s1, align_s2, align_rddata;
e08b748a	56
c65110a8	57	wire next_outbubble;
a02ca509 JW	58	wire next_write_reg;
	59	wire [3:0] next_write_num;
	60	wire [31:0] next_write_data;
74d3729c	61
9a0d0e43 CL	62	reg [1:0] lsr_state = 2'b01, next_lsr_state;
9a0d0e43 CL	63
b783a475	64	reg [15:0] regs, next_regs;
9a0d0e43	65	reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f	66	reg [5:0] offset, prev_offset, offset_sel;
74d3729c	67
9a0d0e43 CL	68	reg [31:0] swp_oldval, next_swp_oldval;
9a0d0e43 CL	69	reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509 JW	70
	71	always @(posedge clk)
	72	begin
	73	outpc <= pc;
	74	outinsn <= insn;
c65110a8 JW	75	outbubble <= next_outbubble;
	76	out_write_reg <= next_write_reg;
	77	out_write_num <= next_write_num;
	78	out_write_data <= next_write_data;
e68b2378	79	regs <= next_regs;
e08b748a	80	prev_reg <= cur_reg;
b114e03f CL	81	prev_offset <= offset;
b114e03f CL	82	prev_raddr <= raddr;
efd1aa13 CL	83	out_cpsr <= next_outcpsr;
efd1aa13 CL	84	out_spsr <= spsr;
9a0d0e43	85	swp_state <= next_swp_state;
a02ca509	86	end
b3bb2fb8 CL	87
	88	always @(*)
	89	begin
	90	addr = 32'hxxxxxxxx;
	91	raddr = 32'hxxxxxxxx;
	92	rd_req = 1'b0;
	93	wr_req = 1'b0;
	94	wr_data = 32'hxxxxxxxx;
	95	busaddr = 32'hxxxxxxxx;
	96	outstall = 1'b0;
a02ca509 JW	97	next_write_reg = write_reg;
	98	next_write_num = write_num;
	99	next_write_data = write_data;
c65110a8	100	next_outbubble = inbubble;
a02ca509	101	outstall = 1'b0;
9a0d0e43	102	next_regs = regs;
979f2bd7	103	cp_req = 1'b0;
43e4332c JW	104	cp_rnw = 1'bx;
43e4332c JW	105	cp_write = 32'hxxxxxxxx;
b114e03f	106	offset = prev_offset;
9a0d0e43 CL	107	next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
	108	next_lsm_state = lsm_state;
	109	next_lsr_state = lsr_state;
	110	next_swp_oldval = swp_oldval;
	111	next_swp_state = swp_state;
	112	cur_reg = prev_reg;
9f082c0b	113
5989b2f5 CL	114	/* XXX shit not given about endianness */
5989b2f5 CL	115	/* TODO ldrh/strh */
b3bb2fb8	116	casez(insn)
5989b2f5 CL	117	`DECODE_ALU_SWP: if(!inbubble) begin
	118	outstall = rw_wait;
	119	next_outbubble = rw_wait;
	120	busaddr = {op0[31:2], 2'b0};
	121	case(swp_state)
	122	2'b01: begin
	123	rd_req = 1'b1;
	124	outstall = 1'b1;
	125	if(!rw_wait) begin
	126	next_swp_state = 2'b10;
	127	next_swp_oldval = rd_data;
9a0d0e43	128	end
9a0d0e43	129	end
5989b2f5 CL	130	2'b10: begin
	131	wr_req = 1'b1;
	132	wr_data = op1;
	133	next_write_reg = 1'b1;
	134	next_write_num = insn[15:12];
	135	next_write_data = swp_oldval;
	136	if(!rw_wait)
	137	next_swp_state = 2'b01;
	138	end
	139	default: begin end
	140	endcase
9a0d0e43	141	end
b3bb2fb8	142	`DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5 CL	143	`DECODE_LDRSTR: if(!inbubble) begin
	144	next_outbubble = rw_wait;
	145	outstall = rw_wait;
	146	addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
	147	raddr = insn[24] ? op0 : addr; /* pre/post increment */
	148	busaddr = {raddr[31:2], 2'b0};
a02ca509	149	/* rotate to correct position */
5989b2f5 CL	150	align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
	151	align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
	152	/* select byte or word */
	153	align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
	154	if(!insn[20]) begin
	155	wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
	156	end
	157	case(lsr_state)
	158	2'b01: begin
	159	rd_req = insn[20];
	160	wr_req = ~insn[20];
	161	if(insn[20]) begin
	162	next_write_reg = 1'b1;
	163	next_write_num = insn[15:12];
	164	next_write_data = align_rddata;
a02ca509	165	end
9a0d0e43	166	if(insn[21]) begin
5989b2f5 CL	167	outstall = 1'b1;
	168	if(!rw_wait)
	169	next_lsr_state = 2'b10;
a02ca509	170	end
b3bb2fb8	171	end
5989b2f5 CL	172	2'b10: begin
	173	next_write_reg = 1'b1;
	174	next_write_num = insn[19:16];
	175	next_write_data = addr;
	176	next_lsr_state = 2'b10;
	177	end
	178	default: begin end
	179	endcase
b3bb2fb8	180	end
5989b2f5 CL	181	/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
5989b2f5 CL	182	`DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43 CL	183	outstall = rw_wait;
	184	next_outbubble = rw_wait;
	185	case(lsm_state)
	186	3'b001: begin
b114e03f CL	187	// next_regs = insn[23] ? op1[15:0] : op1[0:15];
	188	/** verilator can suck my dick */
	189	next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
	190	op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
	191	offset = 6'b0;
9a0d0e43 CL	192	outstall = 1'b1;
9a0d0e43 CL	193	next_lsm_state = 3'b010;
e08b748a	194	end
9a0d0e43 CL	195	3'b010: begin
	196	rd_req = insn[20];
	197	wr_req = ~insn[20];
9f082c0b CL	198	casez(regs)
9f082c0b CL	199	16'b???????????????1: begin
e08b748a	200	cur_reg = 4'h0;
b114e03f	201	next_regs = {regs[15:1], 1'b0};
9f082c0b CL	202	end
9f082c0b CL	203	16'b??????????????10: begin
e08b748a	204	cur_reg = 4'h1;
b114e03f	205	next_regs = {regs[15:2], 2'b0};
9f082c0b CL	206	end
9f082c0b CL	207	16'b?????????????100: begin
e08b748a	208	cur_reg = 4'h2;
b114e03f	209	next_regs = {regs[15:3], 3'b0};
9f082c0b CL	210	end
9f082c0b CL	211	16'b????????????1000: begin
e08b748a	212	cur_reg = 4'h3;
b114e03f	213	next_regs = {regs[15:4], 4'b0};
9f082c0b CL	214	end
9f082c0b CL	215	16'b???????????10000: begin
e08b748a	216	cur_reg = 4'h4;
b114e03f	217	next_regs = {regs[15:5], 5'b0};
9f082c0b CL	218	end
9f082c0b CL	219	16'b??????????100000: begin
e08b748a	220	cur_reg = 4'h5;
b114e03f	221	next_regs = {regs[15:6], 6'b0};
9f082c0b CL	222	end
9f082c0b CL	223	16'b?????????1000000: begin
e08b748a	224	cur_reg = 4'h6;
b114e03f	225	next_regs = {regs[15:7], 7'b0};
9f082c0b CL	226	end
9f082c0b CL	227	16'b????????10000000: begin
e08b748a	228	cur_reg = 4'h7;
b114e03f	229	next_regs = {regs[15:8], 8'b0};
9f082c0b CL	230	end
9f082c0b CL	231	16'b???????100000000: begin
e08b748a	232	cur_reg = 4'h8;
b114e03f	233	next_regs = {regs[15:9], 9'b0};
9f082c0b CL	234	end
9f082c0b CL	235	16'b??????1000000000: begin
e08b748a	236	cur_reg = 4'h9;
b114e03f	237	next_regs = {regs[15:10], 10'b0};
9f082c0b CL	238	end
9f082c0b CL	239	16'b?????10000000000: begin
e08b748a	240	cur_reg = 4'hA;
b114e03f	241	next_regs = {regs[15:11], 11'b0};
9f082c0b CL	242	end
9f082c0b CL	243	16'b????100000000000: begin
e08b748a	244	cur_reg = 4'hB;
b114e03f	245	next_regs = {regs[15:12], 12'b0};
9f082c0b CL	246	end
9f082c0b CL	247	16'b???1000000000000: begin
e08b748a	248	cur_reg = 4'hC;
b114e03f	249	next_regs = {regs[15:13], 13'b0};
9f082c0b CL	250	end
9f082c0b CL	251	16'b??10000000000000: begin
e08b748a	252	cur_reg = 4'hD;
b114e03f	253	next_regs = {regs[15:14], 14'b0};
9f082c0b CL	254	end
9f082c0b CL	255	16'b?100000000000000: begin
e08b748a	256	cur_reg = 4'hE;
b114e03f	257	next_regs = {regs[15], 15'b0};
9f082c0b CL	258	end
9f082c0b CL	259	16'b1000000000000000: begin
e08b748a	260	cur_reg = 4'hF;
9f082c0b CL	261	next_regs = 16'b0;
	262	end
	263	default: begin
e08b748a CL	264	cur_reg = 4'hx;
e08b748a CL	265	next_regs = 16'b0;
9f082c0b CL	266	end
9f082c0b CL	267	endcase
b114e03f	268	cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
efd1aa13 CL	269	if(cur_reg == 4'hF && insn[22]) begin
	270	next_outcpsr = spsr;
	271	end
b114e03f	272
9a0d0e43 CL	273	if(rw_wait) begin
	274	next_regs = regs;
	275	cur_reg = prev_reg;
	276	raddr = prev_raddr;
	277	end
	278	else begin
	279	offset = prev_offset + 6'h4;
	280	offset_sel = insn[24] ? offset : prev_offset;
	281	raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
	282	if(insn[20]) begin
	283	next_write_reg = 1'b1;
	284	next_write_num = cur_reg;
	285	next_write_data = rd_data;
	286	end
b114e03f CL	287	end
	288
	289	st_read = cur_reg;
	290	wr_data = st_data;
b114e03f	291	busaddr = {raddr[31:2], 2'b0};
9a0d0e43 CL	292
	293	outstall = 1'b1;
	294
	295	if(next_regs == 16'b0) begin
	296	next_lsm_state = 3'b100;
	297	end
	298	end
	299	3'b100: begin
	300	next_write_reg = 1'b1;
	301	next_write_num = insn[19:16];
	302	next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
	303	next_lsm_state = 3'b001;
b783a475	304	end
9a0d0e43 CL	305	default: begin end
9a0d0e43 CL	306	endcase
b3bb2fb8	307	end
5989b2f5	308	`DECODE_LDCSTC: if(!inbubble) begin
43e4332c JW	309	$display("WARNING: Unimplemented LDCSTC");
43e4332c JW	310	end
5989b2f5	311	`DECODE_CDP: if(!inbubble) begin
43e4332c JW	312	cp_req = 1;
	313	if (cp_busy) begin
	314	outstall = 1;
	315	next_outbubble = 1;
	316	end
	317	if (!cp_ack) begin
	318	/* XXX undefined instruction trap */
	319	$display("WARNING: Possible CDP undefined instruction");
	320	end
	321	end
5989b2f5	322	`DECODE_MRCMCR: if(!inbubble) begin
43e4332c JW	323	cp_req = 1;
	324	cp_rnw = insn[20] /* L */;
	325	if (insn[20] == 0 /* store to coprocessor */)
	326	cp_write = op0;
	327	else begin
d1d0eb8e JW	328	if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
	329	next_write_reg = 1'b1;
	330	next_write_num = insn[15:12];
	331	next_write_data = cp_read;
	332	end else
	333	next_outcpsr = {cp_read[31:28], cpsr[27:0]};
43e4332c JW	334	end
	335	if (cp_busy) begin
	336	outstall = 1;
	337	next_outbubble = 1;
	338	end
	339	if (!cp_ack) begin
	340	$display("WARNING: Possible MRCMCR undefined instruction");
	341	end
	342	end
b3bb2fb8 CL	343	default: begin end
	344	endcase
	345	end
b3bb2fb8	346	endmodule