system.v: Add debug output for the execute stage.
[firearm.git] / RegFile.v
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1module RegFile(
2 input clk,
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3 input [3:0] read_0,
4 output reg [31:0] rdata_0,
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5 input [3:0] read_1,
6 output reg [31:0] rdata_1,
7 input [3:0] read_2,
8 output reg [31:0] rdata_2,
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9 input [3:0] write,
10 input write_req,
11 input [31:0] write_data
12 );
13
14 reg [31:0] regfile [0:15];
15
16 initial begin
17 regfile[4'h0] = 32'h00000005;
18 regfile[4'h1] = 32'h00000050;
19 regfile[4'h2] = 32'h00000500;
20 regfile[4'h3] = 32'h00005000;
21 regfile[4'h4] = 32'h00050000;
22 regfile[4'h5] = 32'h00500000;
23 regfile[4'h6] = 32'h05000000;
24 regfile[4'h7] = 32'h50000000;
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25 regfile[4'h8] = 32'hA0000000;
26 regfile[4'h9] = 32'h0A000000;
27 regfile[4'hA] = 32'h00A00000;
28 regfile[4'hB] = 32'h000A0000;
29 regfile[4'hC] = 32'h0000A000;
30 regfile[4'hD] = 32'h00000A00;
31 regfile[4'hE] = 32'h000000A0;
32 regfile[4'hF] = 32'h0000000A;
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33 end
34
35 always @(*)
36 begin
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37 if ((read_0 == write) && write_req)
38 rdata_0 = write_data;
39 else
40 rdata_0 = regfile[read_0];
41
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42 if ((read_1 == write) && write_req)
43 rdata_1 = write_data;
44 else
45 rdata_1 = regfile[read_1];
46
47 if ((read_2 == write) && write_req)
48 rdata_2 = write_data;
49 else
50 rdata_2 = regfile[read_2];
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51 end
52
53 always @(posedge clk)
54 if (write_req)
55 regfile[write] <= write_data;
56endmodule
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