[firearm.git] / Decode.v

`include "ARM_Constants.v"

module Decode(
	input clk,
	input [31:0] insn,
	input [31:0] inpc,
	input [31:0] incpsr,
	output reg [31:0] op0,
	output reg [31:0] op1,
	output reg [31:0] op2,
	output reg carry,

	output reg [3:0] read_0,
	output reg [3:0] read_1,
	output reg [3:0] read_2,
	input [31:0] rdata_0,
	input [31:0] rdata_1,
	input [31:0] rdata_2
	);

	wire [31:0] regs0, regs1, regs2;
	reg [31:0] rpc;
	reg [31:0] op0_out, op1_out, op2_out;
	reg carry_out;

	/* shifter stuff */
	wire [31:0] shift_oper;
	wire [31:0] shift_res;
	wire shift_cflag_out;
	wire [31:0] rotate_res;

	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */

	IREALLYHATEARMSHIFT blowme(.insn(insn),
	                           .operand(regs1),
	                           .reg_amt(regs2),
	                           .cflag_in(incpsr[`CPSR_C]),
	                           .res(shift_res),
	                           .cflag_out(shift_cflag_out));

	SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
	                      .amt(insn[11:8]),
	                      .res(rotate_res));

	always @(*)
		casez (insn)
		32'b????000000??????????????1001????,	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
//		32'b????00001???????????????1001????,	/* Multiply long */
		32'b????00010?001111????000000000000,	/* MRS (Transfer PSR to register) */
		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
		32'b????00?10?1010001111????????????,	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		32'b????00010?00????????00001001????,	/* Atomic swap */
		32'b????000100101111111111110001????,	/* Branch and exchange */
		32'b????000??0??????????00001??1????,	/* Halfword transfer - register offset */
		32'b????000??1??????????00001??1????,	/* Halfword transfer - register offset */
		32'b????011????????????????????1????,	/* Undefined. I hate ARM */
		32'b????01??????????????????????????,	/* Single data transfer */
		32'b????100?????????????????????????,	/* Block data transfer */
		32'b????101?????????????????????????,	/* Branch */
		32'b????110?????????????????????????,	/* Coprocessor data transfer */
		32'b????1110???????????????????0????,	/* Coprocessor data op */
		32'b????1110???????????????????1????,	/* Coprocessor register transfer */
		32'b????1111????????????????????????:	/* SWI */
			rpc = inpc - 8;
		32'b????00??????????????????????????:	/* ALU */
			rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
		default:				/* X everything else out */
			rpc = 32'hxxxxxxxx;
		endcase

	always @(*) begin
		read_0 = 4'hx;
		read_1 = 4'hx;
		read_2 = 4'hx;
		
		casez (insn)
		32'b????000000??????????????1001????:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			read_0 = insn[15:12]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs */
		end
//		32'b????00001???????????????1001????,	/* Multiply long */
//			read_0 = insn[11:8]; /* Rn */
//			read_1 = insn[3:0];   /* Rm */
//			read_2 = 4'b0;       /* anyus */
		32'b????00010?001111????000000000000:	/* MRS (Transfer PSR to register) */
		begin end
		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
		32'b????00?10?1010001111????????????:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
			read_0 = insn[3:0];	/* Rm */
		32'b????00??????????????????????????:	/* ALU */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs for shift */
		end
		32'b????00010?00????????00001001????:	/* Atomic swap */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
		end
		32'b????000100101111111111110001????:	/* Branch and exchange */
			read_0 = insn[3:0];   /* Rn */
		32'b????000??0??????????00001??1????:	/* Halfword transfer - register offset */
		begin
			read_0 = insn[19:16];
			read_1 = insn[3:0];
		end
		32'b????000??1??????????00001??1????:	/* Halfword transfer - immediate offset */
		begin
			read_0 = insn[19:16];
		end
		32'b????011????????????????????1????:	/* Undefined. I hate ARM */
		begin end
		32'b????01??????????????????????????:	/* Single data transfer */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
		end
		32'b????100?????????????????????????:	/* Block data transfer */
			read_0 = insn[19:16];
		32'b????101?????????????????????????:	/* Branch */
		begin end
		32'b????110?????????????????????????:	/* Coprocessor data transfer */
			read_0 = insn[19:16];
		32'b????1110???????????????????0????:	/* Coprocessor data op */
		begin end
		32'b????1110???????????????????1????:	/* Coprocessor register transfer */
			read_0 = insn[15:12];
		32'b????1111????????????????????????:	/* SWI */
		begin end
		default:
			$display("Undecoded instruction");
		endcase
	end
	
	always @(*) begin
		op0_out = 32'hxxxxxxxx;
		op1_out = 32'hxxxxxxxx;
		op2_out = 32'hxxxxxxxx;
		carry_out = 1'bx;
		casez (insn)
		32'b????000000??????????????1001????: begin /* Multiply */
			op0_out = regs0;
			op1_out = regs1;
			op2_out = regs2;
		end
//		32'b????00001???????????????1001????: begin /* Multiply long */
//			op1_res = regs1;
//		end
		32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
		end
        	32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
        		op0_out = regs0;
        	end
                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
                	if(insn[25]) begin     /* the constant case */
				op0_out = rotate_res;
			end else begin
				op0_out = regs0;
			end
                end
		32'b????00??????????????????????????: begin /* ALU */
			op0_out = regs0;
			if(insn[25]) begin     /* the constant case */
				carry_out = incpsr[`CPSR_C];
				op1_out = rotate_res;
			end else begin
				carry_out = shift_cflag_out;
				op1_out = shift_res;
			end
		end
		32'b????00010?00????????00001001????: begin /* Atomic swap */
			op0_out = regs0;
			op1_out = regs1;
		end
		32'b????000100101111111111110001????: begin /* Branch and exchange */
			op0_out = regs0;
		end
		32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
			op0_out = regs0;
			op1_out = regs1;
		end
		32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
			op0_out = regs0;
			op1_out = {24'b0, insn[11:8], insn[3:0]};
		end
		32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
			/* eat shit */
		end
		32'b????01??????????????????????????: begin /* Single data transfer */
			op0_out = regs0;
			if(insn[25]) begin
				op1_out = {20'b0, insn[11:0]};
				carry_out = incpsr[`CPSR_C];
			end else begin
				op1_out = shift_res;
				carry_out = shift_cflag_out;
			end
		end
		32'b????100?????????????????????????: begin /* Block data transfer */
			op0_out = regs0;
			op1_out = {16'b0, insn[15:0]};
		end
		32'b????101?????????????????????????: begin /* Branch */
			op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
		end
		32'b????110?????????????????????????: begin /* Coprocessor data transfer */
			op0_out = regs0;
			op1_out = {24'b0, insn[7:0]};
		end
		32'b????1110???????????????????0????: begin /* Coprocessor data op */
		end
		32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
			op0_out = regs0;
		end
		32'b????1111????????????????????????: begin /* SWI */
		end
		default: begin end
		endcase
	end

	always @ (posedge clk) begin
		op0 <= op0_out;   /* Rn - always */
		op1 <= op1_out; /* 'operand 2' - Rm */
		op2 <= op2_out;   /* thirdedge - Rs */
		carry <= carry_out;
	end

endmodule

module IREALLYHATEARMSHIFT(
	input [31:0] insn,
	input [31:0] operand,
	input [31:0] reg_amt,
	input cflag_in,
	output reg [31:0] res,
	output reg cflag_out
);
	wire [5:0] shift_amt;
	reg is_arith, is_rot;
	wire rshift_cout;
	wire [31:0] rshift_res;

	assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
	                           : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */

	SuckLessShifter biteme(.oper(operand),
	                       .carryin(cflag_in),
	                       .amt(shift_amt),
	                       .is_arith(is_arith),
	                       .is_rot(is_rot),
	                       .res(rshift_res),
	                       .carryout(rshift_cout));

	always @(*)
		case (insn[6:5])
		`SHIFT_LSL: begin
			/* meaningless */
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_LSR: begin
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_ASR: begin
			is_rot = 1'b0;
			is_arith = 1'b1;
		end
		`SHIFT_ROR: begin
			is_rot = 1'b1;
			is_arith = 1'b0;
		end
		endcase

	always @(*)
		case (insn[6:5]) /* shift type */
		`SHIFT_LSL:
			{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
		`SHIFT_LSR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ASR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ROR: begin
			if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
				res = {cflag_in, operand[31:1]};
				cflag_out = operand[0];
			end else begin
				res = rshift_res;
				cflag_out = rshift_cout;
			end
		end
		endcase
endmodule

module SuckLessShifter(
	input [31:0] oper,
	input carryin,
	input [5:0] amt,
	input is_arith,
	input is_rot,
	output wire [31:0] res,
	output wire carryout
);

	wire [32:0] stage1, stage2, stage3, stage4, stage5;

	wire pushbits = is_arith & oper[31];

	/* do a barrel shift */
	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;

endmodule

module SuckLessRotator(
	input [31:0] oper,
	input [3:0] amt,
	output wire [31:0] res
);

	wire [31:0] stage1, stage2, stage3;
	assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
	assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
	assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
	assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;

endmodule
Commit	Line	Data
26049339 CL	1	`include "ARM_Constants.v"
26049339 CL	2
bae77231 CL	3	module Decode(
bae77231 CL	4	input clk,
be64a9df	5	input [31:0] insn,
bae77231	6	input [31:0] inpc,
821617bb	7	input [31:0] incpsr,
bae77231 CL	8	output reg [31:0] op0,
	9	output reg [31:0] op1,
	10	output reg [31:0] op2,
42c1e610	11	output reg carry,
bae77231	12
fbe84cc1 JW	13	output reg [3:0] read_0,
	14	output reg [3:0] read_1,
	15	output reg [3:0] read_2,
821617bb JW	16	input [31:0] rdata_0,
	17	input [31:0] rdata_1,
	18	input [31:0] rdata_2
bae77231 CL	19	);
bae77231 CL	20
fbe84cc1 JW	21	wire [31:0] regs0, regs1, regs2;
	22	reg [31:0] rpc;
	23	reg [31:0] op0_out, op1_out, op2_out;
	24	reg carry_out;
bae77231 CL	25
	26	/* shifter stuff */
	27	wire [31:0] shift_oper;
	28	wire [31:0] shift_res;
	29	wire shift_cflag_out;
a0c8a75c	30	wire [31:0] rotate_res;
bae77231	31
821617bb JW	32	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	33	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	34	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231	35
e2c5d224 CL	36	IREALLYHATEARMSHIFT blowme(.insn(insn),
	37	.operand(regs1),
	38	.reg_amt(regs2),
	39	.cflag_in(incpsr[`CPSR_C]),
	40	.res(shift_res),
	41	.cflag_out(shift_cflag_out));
	42
a0c8a75c CL	43	SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
	44	.amt(insn[11:8]),
	45	.res(rotate_res));
	46
be64a9df JW	47	always @(*)
	48	casez (insn)
	49	32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	50	// 32'b????00001???????????????1001????, /* Multiply long */
	51	32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
	52	32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
	53	32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
	54	32'b????00010?00????????00001001????, /* Atomic swap */
0bc7ede9	55	32'b????000100101111111111110001????, /* Branch and exchange */
be64a9df JW	56	32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
	57	32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
	58	32'b????011????????????????????1????, /* Undefined. I hate ARM */
	59	32'b????01??????????????????????????, /* Single data transfer */
	60	32'b????100?????????????????????????, /* Block data transfer */
	61	32'b????101?????????????????????????, /* Branch */
	62	32'b????110?????????????????????????, /* Coprocessor data transfer */
	63	32'b????1110???????????????????0????, /* Coprocessor data op */
	64	32'b????1110???????????????????1????, /* Coprocessor register transfer */
	65	32'b????1111????????????????????????: /* SWI */
	66	rpc = inpc - 8;
	67	32'b????00??????????????????????????: /* ALU */
	68	rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
	69	default: /* X everything else out */
	70	rpc = 32'hxxxxxxxx;
	71	endcase
bae77231	72
326fd4c3 JW	73	always @(*) begin
	74	read_0 = 4'hx;
	75	read_1 = 4'hx;
	76	read_2 = 4'hx;
	77
0bc7ede9 JW	78	casez (insn)
0bc7ede9 JW	79	32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3	80	begin
0bc7ede9	81	read_0 = insn[15:12]; /* Rn */
326fd4c3 JW	82	read_1 = insn[3:0]; /* Rm */
	83	read_2 = insn[11:8]; /* Rs */
	84	end
0bc7ede9 JW	85	// 32'b????00001???????????????1001????, /* Multiply long */
0bc7ede9 JW	86	// read_0 = insn[11:8]; /* Rn */
326fd4c3 JW	87	// read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	88	// read_2 = 4'b0; /* anyus */
42c1e610 JW	89	32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
42c1e610 JW	90	begin end
0bc7ede9 JW	91	32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
0bc7ede9 JW	92	32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
42c1e610	93	read_0 = insn[3:0]; /* Rm */
0bc7ede9	94	32'b????00??????????????????????????: /* ALU */
326fd4c3	95	begin
0bc7ede9	96	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	97	read_1 = insn[3:0]; /* Rm */
	98	read_2 = insn[11:8]; /* Rs for shift */
	99	end
0bc7ede9	100	32'b????00010?00????????00001001????: /* Atomic swap */
326fd4c3	101	begin
0bc7ede9	102	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	103	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	104	end
0bc7ede9 JW	105	32'b????000100101111111111110001????: /* Branch and exchange */
	106	read_0 = insn[3:0]; /* Rn */
	107	32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
326fd4c3	108	begin
0bc7ede9	109	read_0 = insn[19:16];
326fd4c3 JW	110	read_1 = insn[3:0];
	111	end
	112	32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */
	113	begin
0bc7ede9	114	read_0 = insn[19:16];
326fd4c3	115	end
0bc7ede9	116	32'b????011????????????????????1????: /* Undefined. I hate ARM */
326fd4c3	117	begin end
0bc7ede9	118	32'b????01??????????????????????????: /* Single data transfer */
326fd4c3	119	begin
0bc7ede9	120	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	121	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	122	end
0bc7ede9 JW	123	32'b????100?????????????????????????: /* Block data transfer */
	124	read_0 = insn[19:16];
	125	32'b????101?????????????????????????: /* Branch */
326fd4c3	126	begin end
0bc7ede9 JW	127	32'b????110?????????????????????????: /* Coprocessor data transfer */
0bc7ede9 JW	128	read_0 = insn[19:16];
42c1e610 JW	129	32'b????1110???????????????????0????: /* Coprocessor data op */
	130	begin end
	131	32'b????1110???????????????????1????: /* Coprocessor register transfer */
	132	read_0 = insn[15:12];
0bc7ede9	133	32'b????1111????????????????????????: /* SWI */
326fd4c3	134	begin end
b215c5ff	135	default:
326fd4c3	136	$display("Undecoded instruction");
b215c5ff	137	endcase
326fd4c3	138	end
b215c5ff	139
326fd4c3	140	always @(*) begin
42c1e610 JW	141	op0_out = 32'hxxxxxxxx;
	142	op1_out = 32'hxxxxxxxx;
	143	op2_out = 32'hxxxxxxxx;
	144	carry_out = 1'bx;
be64a9df	145	casez (insn)
bae77231	146	32'b????000000??????????????1001????: begin /* Multiply */
42c1e610 JW	147	op0_out = regs0;
	148	op1_out = regs1;
	149	op2_out = regs2;
bae77231	150	end
b215c5ff JW	151	// 32'b????00001???????????????1001????: begin /* Multiply long */
	152	// op1_res = regs1;
	153	// end
bae77231	154	32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
bae77231 CL	155	end
bae77231 CL	156	32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
42c1e610	157	op0_out = regs0;
bae77231	158	end
42c1e610 JW	159	32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
42c1e610 JW	160	if(insn[25]) begin /* the constant case */
a0c8a75c	161	op0_out = rotate_res;
42c1e610 JW	162	end else begin
	163	op0_out = regs0;
	164	end
bae77231 CL	165	end
bae77231 CL	166	32'b????00??????????????????????????: begin /* ALU */
42c1e610	167	op0_out = regs0;
be64a9df	168	if(insn[25]) begin /* the constant case */
42c1e610	169	carry_out = incpsr[`CPSR_C];
a0c8a75c	170	op1_out = rotate_res;
bae77231	171	end else begin
42c1e610 JW	172	carry_out = shift_cflag_out;
42c1e610 JW	173	op1_out = shift_res;
bae77231 CL	174	end
	175	end
	176	32'b????00010?00????????00001001????: begin /* Atomic swap */
42c1e610 JW	177	op0_out = regs0;
42c1e610 JW	178	op1_out = regs1;
bae77231 CL	179	end
bae77231 CL	180	32'b????000100101111111111110001????: begin /* Branch and exchange */
42c1e610	181	op0_out = regs0;
bae77231 CL	182	end
bae77231 CL	183	32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
42c1e610 JW	184	op0_out = regs0;
42c1e610 JW	185	op1_out = regs1;
bae77231 CL	186	end
bae77231 CL	187	32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
42c1e610 JW	188	op0_out = regs0;
42c1e610 JW	189	op1_out = {24'b0, insn[11:8], insn[3:0]};
bae77231 CL	190	end
	191	32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
	192	/* eat shit */
	193	end
	194	32'b????01??????????????????????????: begin /* Single data transfer */
42c1e610	195	op0_out = regs0;
be64a9df	196	if(insn[25]) begin
42c1e610 JW	197	op1_out = {20'b0, insn[11:0]};
42c1e610 JW	198	carry_out = incpsr[`CPSR_C];
bae77231	199	end else begin
42c1e610 JW	200	op1_out = shift_res;
42c1e610 JW	201	carry_out = shift_cflag_out;
bae77231 CL	202	end
	203	end
	204	32'b????100?????????????????????????: begin /* Block data transfer */
42c1e610 JW	205	op0_out = regs0;
42c1e610 JW	206	op1_out = {16'b0, insn[15:0]};
bae77231 CL	207	end
bae77231 CL	208	32'b????101?????????????????????????: begin /* Branch */
42c1e610	209	op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231 CL	210	end
bae77231 CL	211	32'b????110?????????????????????????: begin /* Coprocessor data transfer */
42c1e610 JW	212	op0_out = regs0;
42c1e610 JW	213	op1_out = {24'b0, insn[7:0]};
bae77231 CL	214	end
bae77231 CL	215	32'b????1110???????????????????0????: begin /* Coprocessor data op */
bae77231 CL	216	end
bae77231 CL	217	32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
42c1e610	218	op0_out = regs0;
bae77231 CL	219	end
bae77231 CL	220	32'b????1111????????????????????????: begin /* SWI */
bae77231	221	end
26049339	222	default: begin end
bae77231 CL	223	endcase
	224	end
	225
	226	always @ (posedge clk) begin
42c1e610 JW	227	op0 <= op0_out; /* Rn - always */
	228	op1 <= op1_out; /* 'operand 2' - Rm */
	229	op2 <= op2_out; /* thirdedge - Rs */
	230	carry <= carry_out;
bae77231 CL	231	end
	232
	233	endmodule
	234
e2c5d224	235	module IREALLYHATEARMSHIFT(
bae77231 CL	236	input [31:0] insn,
	237	input [31:0] operand,
	238	input [31:0] reg_amt,
	239	input cflag_in,
fbe84cc1 JW	240	output reg [31:0] res,
fbe84cc1 JW	241	output reg cflag_out
bae77231	242	);
bae77231	243	wire [5:0] shift_amt;
f61f8d6f JW	244	reg is_arith, is_rot;
	245	wire rshift_cout;
	246	wire [31:0] rshift_res;
e2c5d224 CL	247
	248	assign shift_amt = insn[4] ? {\|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
	249	: {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231	250
e2c5d224 CL	251	SuckLessShifter biteme(.oper(operand),
	252	.carryin(cflag_in),
	253	.amt(shift_amt),
	254	.is_arith(is_arith),
	255	.is_rot(is_rot),
	256	.res(rshift_res),
	257	.carryout(rshift_cout));
bae77231	258
821617bb	259	always @(*)
e2c5d224 CL	260	case (insn[6:5])
e2c5d224 CL	261	`SHIFT_LSL: begin
e5fb7d86	262	/* meaningless */
e2c5d224 CL	263	is_rot = 1'b0;
e2c5d224 CL	264	is_arith = 1'b0;
26049339	265	end
e2c5d224 CL	266	`SHIFT_LSR: begin
	267	is_rot = 1'b0;
	268	is_arith = 1'b0;
	269	end
	270	`SHIFT_ASR: begin
	271	is_rot = 1'b0;
	272	is_arith = 1'b1;
	273	end
	274	`SHIFT_ROR: begin
	275	is_rot = 1'b1;
	276	is_arith = 1'b0;
	277	end
	278	endcase
	279
821617bb	280	always @(*)
26049339	281	case (insn[6:5]) /* shift type */
e2c5d224 CL	282	`SHIFT_LSL:
e2c5d224 CL	283	{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231	284	`SHIFT_LSR: begin
e2c5d224 CL	285	res = rshift_res;
e2c5d224 CL	286	cflag_out = rshift_cout;
bae77231 CL	287	end
bae77231 CL	288	`SHIFT_ASR: begin
e2c5d224 CL	289	res = rshift_res;
e2c5d224 CL	290	cflag_out = rshift_cout;
bae77231 CL	291	end
bae77231 CL	292	`SHIFT_ROR: begin
e2c5d224	293	if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231 CL	294	res = {cflag_in, operand[31:1]};
bae77231 CL	295	cflag_out = operand[0];
e5fb7d86	296	end else begin
e2c5d224 CL	297	res = rshift_res;
e2c5d224 CL	298	cflag_out = rshift_cout;
bae77231 CL	299	end
bae77231 CL	300	end
26049339	301	endcase
bae77231	302	endmodule
e2c5d224 CL	303
	304	module SuckLessShifter(
	305	input [31:0] oper,
	306	input carryin,
	307	input [5:0] amt,
	308	input is_arith,
	309	input is_rot,
f61f8d6f JW	310	output wire [31:0] res,
f61f8d6f JW	311	output wire carryout
e2c5d224 CL	312	);
	313
	314	wire [32:0] stage1, stage2, stage3, stage4, stage5;
	315
e5fb7d86	316	wire pushbits = is_arith & oper[31];
e2c5d224 CL	317
	318	/* do a barrel shift */
	319	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10 CL	320	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
	321	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
	322	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
	323	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
	324	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224 CL	325
e2c5d224 CL	326	endmodule
a0c8a75c CL	327
	328	module SuckLessRotator(
	329	input [31:0] oper,
	330	input [3:0] amt,
f61f8d6f	331	output wire [31:0] res
a0c8a75c CL	332	);
	333
	334	wire [31:0] stage1, stage2, stage3;
	335	assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
	336	assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
	337	assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
	338	assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
	339
	340	endmodule